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8-channel, 24-bit, simultaneous sampling adc data sheet AD7779 rev. 0 document feedbac k information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical suppor t www.analog.com features 8-channel, 24-bit simultaneous sampling analog-to-digital converter (adc) single-ended or true differential inputs programmable gain amplifier (pga) per channel (gains of 1, 2, 4, and 8) low dc input current: 4 na up to 16 ksps output data rate (odr) per channel programmable odrs and bandwidth sample rate converter (src) for coherent sampling sampling rate resolution up to 15.2 sps low latency sinc3 filter path adjustable phase synchronization internal 2.5 v reference two power modes high resolution mode low power mode optimizes power dissipation and performance low resolution successive approximation (sar) adc for system and chip diagnostics power supply bipolar (1.65 v) or unipolar (3.3 v) supplies digital input/output (i/o) supply: 1.8 v to 3.6 v performance temperature range: C40c to +105c functional temperature range: C40c to +125c performance combined ac and dc performance 108 db signal-to-noise ratio (snr)/dynamic range at 16 ksps in high resolution mode ?109 db total harmonic distortion (thd) 7 ppm integral nonlinearity (inl) 40 v offset error 0.1% gain error 10 ppm/c typical temperature coefficient applications circuit breakers general-purpose data acquisition electroencephalography (eeg) industrial process control general description the AD7779 is an 8-channel, simultaneous sampling adc. there are eight full sigma-delta (-) adcs on chip. the AD7779 provides an ultralow input current to allow direct sensor connection. each input channel has a programmable gain stage allowing gains of 1, 2, 4, and 8 to map lower amplitude sensor outputs into the full-scale adc input range, maximizing the dynamic range of the signal chain. the AD7779 accepts v ref from 1 v up to 3.6 v. the analog inputs accept unipolar (0 v to v ref ) or true bipolar (v ref /2 v) analog input signals with 3.3 v or 1.65 v analog supply voltages, respectively. the analog inputs can be configured to accept true differential or single-ended signals to match different sensor output configurations. each channel contains an adc modulator and a sinc3, low latency digital filter. an src is provided to allow fine resolution control over the AD7779 odr. this control can be used in applications where the odr resolution is required to maintain coherency with 0.01 hz changes in the line frequency. the src is programmable through the serial port interface (spi). the AD7779 implements two different interfaces: a data output interface and spi control interface. the adc data output interface is dedicated to trans- mitting the adc conversion results from the AD7779 to the processor. the spi interface is used to write to and read from the AD7779 configuration registers and for the control and reading of data from the sar adc. the spi interface can also be configured to output the - conversion data. the AD7779 includes a 12-bit sar adc. this adc can be used for AD7779 diagnostics without having to decommission one of the - adc channels dedicated to system measurement func- tions. with the use of an external multiplexer, which can be controlled through the three general-purpose inputs/outputs pins (gpios), and signal conditioning, the sar adc can be used to validate the - adc measurements in applications where functional safety is required. in addition, the AD7779 sar adc includes as an internal multiplexer to sense internal nodes. the AD7779 contains a 2.5 v reference and reference buffer. the reference has a typical temperature coefficient of 10 ppm/c. the AD7779 offers two modes of operation: high resolution mode and low power mode. high resolution mode provides a higher dynamic range while consuming 10.75 mw per channel; low power mode consumes just 3.37 mw per channel at a reduced dynamic range specification. the specified operating temperature range is ?40c to +105c, although the device is operational up to +125c. note that throughout this data sheet, certain terms are used to refer to either the multifunction pins or a range of pins. the multi- function pins, such as dclk0/sdo, are referred to either by the entire pin name or by a single function of the pin, for example, dclk0, when only that function is relevant. in the case of ranges of pins, avssx refers to t he fol lowi ng pi ns: avs s1a, avss1b, avss2a, avss2b, avss3, and avss4.
AD7779 data sheet rev. 0 | page 2 of 97 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 3 ? functional block diagram .............................................................. 4 ? specifications ..................................................................................... 5 ? doutx timing characterististics ............................................. 9 ? spi timing characterististics ................................................... 10 ? synchronization pins and reset timing characteristics ...... 11 ? sar adc timing characterististics ....................................... 12 ? gpio src update timing characterististics ......................... 12 ? absolute maximum ratings .......................................................... 13 ? thermal resistance .................................................................... 13 ? esd caution ................................................................................ 13 ? pin configuration and function descriptions ........................... 14 ? typical performance characteristics ........................................... 17 ? terminology .................................................................................... 30 ? rms noise and resolution ............................................................ 31 ? high resolution mode ............................................................... 31 ? low power mode ........................................................................ 31 ? theory of operation ...................................................................... 32 ? analog inputs .............................................................................. 32 ? transfer function ....................................................................... 33 ? core signal chain ....................................................................... 34 ? capacitive pga ........................................................................... 34 ? internal reference and reference buffers ............................... 34 ? integrated ldos ......................................................................... 35 ? clocking and sampling .............................................................. 35 ? digital reset and synchronization pins .................................. 35 ? digital filtering ........................................................................... 36 ? shutdown mode .......................................................................... 36 ? controlling the AD7779 ............................................................ 37 ? pin control mode ....................................................................... 37 ? spi control .................................................................................. 39 ? digital spi interface ................................................................... 42 ? diagnostics and monitoring ......................................................... 45 ? self diagnostics error ................................................................ 45 ? monitoring using the AD7779 sar adc (spi control mode) ........................................................................................... 46 ? - adc diagnostics (spi control mode) ............................ 48 ? ? - output data............................................................................. 49 ? adc conversion outputheader and data ........................ 49 ? sample rate converter (src) (spi control mode) ............ 50 ? data output interface ................................................................ 51 ? calculating the crc checksum .............................................. 56 ? register summary .......................................................................... 57 ? register details ............................................................................... 61 ? channel 0 configuration register ........................................... 61 ? channel 1 configuration register ........................................... 61 ? channel 2 configuration register ........................................... 62 ? channel 3 configuration register ........................................... 62 ? channel 4 configuration register ........................................... 63 ? channel 5 configuration register ........................................... 63 ? channel 6 configuration register ........................................... 64 ? channel 7 configuration register ........................................... 64 ? disable clocks to adc channel register .............................. 65 ? channel 0 sync offset register ................................................ 65 ? channel 1 sync offset register ................................................ 65 ? channel 2 sync offset register ................................................ 66 ? channel 3 sync offset register ................................................ 66 ? channel 4 sync offset register ................................................ 66 ? channel 5 sync offset register ................................................ 66 ? channel 6 sync offset register ................................................ 67 ? channel 7 sync offset register ................................................ 67 ? general user configuration 1 register ................................... 67 ? general user configuration 2 register ................................... 68 ? general user configuration 3 register ................................... 69 ? data output format register ................................................... 69 ? main adc meter and reference mux control register ...... 70 ? global diagnostics mux register ............................................. 71 ? gpio configuration register ................................................... 72 ? gpio data register .................................................................... 72 ? buffer configuration 1 register ............................................... 72 ? buffer configuration 2 register ............................................... 73 ? channel 0 offset upper byte register..................................... 73 ? channel 0 offset middle byte register ................................... 73 ? channel 0 offset lower byte register ..................................... 74 ? channel 0 gain upper byte register ....................................... 74 ? channel 0 gain middle byte register ..................................... 74 ? channel 0 gain lower byte register ....................................... 74 ?
data sheet AD7779 rev. 0 | page 3 of 97 channel 1 offset upper byte register ..................................... 75 ? channel 1 offset middle byte register .................................... 75 ? channel 1 offset lower byte register ..................................... 75 ? channel 1 gain upper byte register........................................ 75 ? channel 1 gain middle byte register ...................................... 76 ? channel 1 gain lower byte register ........................................ 76 ? channel 2 offset upper byte register ..................................... 76 ? channel 2 offset middle byte register .................................... 76 ? channel 2 offset lower byte register ..................................... 77 ? channel 2 gain upper byte register........................................ 77 ? channel 2 gain middle byte register ...................................... 77 ? channel 2 gain lower byte register ........................................ 77 ? channel 3 offset upper byte register ..................................... 78 ? channel 3 offset middle byte register .................................... 78 ? channel 3 offset lower byte register ..................................... 78 ? channel 3 gain upper byte register........................................ 78 ? channel 3 gain middle byte register ...................................... 79 ? channel 3 gain lower byte register ........................................ 79 ? channel 4 offset upper byte register ..................................... 79 ? channel 4 offset middle byte register .................................... 79 ? channel 4 offset lower byte register ..................................... 80 ? channel 4 gain upper byte register........................................ 80 ? channel 4 gain middle byte register ...................................... 80 ? channel 4 gain lower byte register ........................................ 80 ? channel 5 offset upper byte register ..................................... 81 ? channel 5 offset middle byte register .................................... 81 ? channel 5 offset lower byte register ..................................... 81 ? channel 5 gain upper byte register........................................ 81 ? channel 5 gain middle byte register ...................................... 82 ? channel 5 gain lower byte register ........................................ 82 ? channel 6 offset upper byte register ..................................... 82 ? channel 6 offset middle byte register .................................... 82 ? channel 6 offset lower byte register ..................................... 83 ? channel 6 gain upper byte register........................................ 83 ? channel 6 gain middle byte register ...................................... 83 ? channel 6 gain lower byte register ....................................... 83 ? channel 7 offset upper byte register ..................................... 84 ? channel 7 offset middle byte register .................................... 84 ? channel 7 offset lower byte register ..................................... 84 ? channel 7 gain upper byte register ....................................... 84 ? channel 7 gain middle byte register ...................................... 85 ? channel 7 gain lower byte register ....................................... 85 ? channel 0 status register .......................................................... 85 ? channel 1 status register .......................................................... 86 ? channel 2 status register .......................................................... 86 ? channel 3 status register .......................................................... 87 ? channel 4 status register .......................................................... 87 ? channel 5 status register .......................................................... 88 ? channel 6 status register .......................................................... 88 ? channel 7 status register .......................................................... 89 ? channel 0/channel 1 dsp errors register.............................. 89 ? channel 2/channel 3 dsp errors register.............................. 90 ? channel 4/channel 5 dsp errors register.............................. 90 ? channel 6/channel 7 dsp errors register.............................. 91 ? channel 0 to channel 7 error register enable register........ 91 ? general errors register 1 ........................................................... 92 ? general errors register 1 enable .............................................. 92 ? general errors register 2 ........................................................... 93 ? general errors register 2 enable .............................................. 93 ? error status register 1 ................................................................ 94 ? error status register 2 ................................................................ 94 ? error status register 3 ................................................................ 95 ? decimation rate (n) msb register ......................................... 95 ? decimation rate (n) lsb register ........................................... 95 ? decimation rate (if) msb register ......................................... 96 ? decimation rate (if) lsb register .......................................... 96 ? src load source and load update register .......................... 96 ? outline dimensions ........................................................................ 97 ? ordering guide ........................................................................... 97 ? revision history 2 /16revision 0 : initial version
AD7779 data sheet rev. 0 | page 4 of 97 functional block diagram avdd1x ref_out refx+ vcm a vdd2 avssx avdd4 convst_sar iovdd a regxcap dregcap clock manager xtal1 xtal2/mclk sync_in sync_out start refx? dclk drdy dout3 dout2 dout1 dout0 format1 format0 mode3/alert mode2/gpio2 mode1/gpio1 mode0/gpio0 alert/cs dclk2/sclk dclk1/sdi dclk0/sdo reset -? adc ain0+ ain0? 280mv p-p -? adc references ext_ref int_ref ain1+ ain1? -? adc references ain2+ ain2? -? adc references ain3+ ain3? -? adc references ain4+ ain4? -? adc references ain5+ ain5? references ain6+ ain6? references diagnostic inputs ain7+ ain7? sinc3/ src filter gain offset common- mode voltage analog ldo 2.5v ref sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset sinc3/ src filter gain offset -? adc -? adc auxain+ auxain? data output interface register map and logic control hardware mode configuration spi interface AD7779 sar adc digital ldo 13295-001 pga pga pga pga pga pga pga pga figure 1.
data sheet AD7779 rev. 0 | page 5 of 97 specifications avdd1x = +1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd (single-supply operation), avdd2x ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v avssx (internal/external), master clock (mclk) = 8192 khz for high resolution mode and 4096 khz for low power mode, odr = 16 khz for high resolution mode and 4 khz for low powe r mode; all specifications at t min to t max , unless otherwise noted. table 1. parameter test conditions/comments min typ max unit analog inputs differential input voltage range v ref = (refx+ ? refx?) v ref /pga gain v single-ended input voltage range 0 to v ref /pga gain v ainx common-mode input range avssx + 0.10 (avdd1x + avssx)/2 avdd1x ? 0.10 v absolute ainx voltage limits avssx + 0.10 avdd1x ? 0.10 dc input current single-ended hp, mclk = 8192 khz 4 na l ow power mode, mclk = 4096 khz 1.5 na differential hp, mclk = 8192 khz 1.5 na l ow power mode, mclk = 4096 khz 0.6 na input current drift 50 pa/c ac input capacitance 8 pf pga gain settings 1, 2, 4, or 8 bandwidth small signal, high resolution mode 2 mhz small signal , low power mode 512 khz l arge signal, high resolution mode 5 khz large signa l, low power mode 1.5 khz reference internal initial accuracy ref_out, t a = 25c 2.5 ? 0.2% 2.5 2.5 + 0.2% v temperature coefficient 10 ppm/c reference load current, i l ?10 +10 ma dc power supply rejection line regulation 95 db load regulation, ?v out /?i l 100 v/ma voltage noise e n p-p , 0.1 hz to 10 hz 6.8 v rms voltage noise density e n , 1 khz, 2.5 v reference 273.5 nv/hz turn on settling time 100 nf 1.5 ms external input voltage v ref = (refx+ ? refx?) 1 2.5 avdd1x v buffer headroom avssx + 0.1 avdd1x ? 0.1 refx? input voltage avssx avdd1x C refx+ v average refx input current current per channel r eference buffer disabled, high resolution mode 18 a/v r eference buffer precharge mode (pre-q), high resolution mode 600 na/v r eference buffer disabled, low power mode 4.5 a/v r eference buffer pre-q, low power mode 100 na/v
AD7779 data sheet rev. 0 | page 6 of 97 parameter test conditions/comments min typ max unit reference buffer enabled, high resolution mode 10 na/v reference buffer enabled, low power mode 5 na/v temperature range specified performance t min to t max ?40 +105 c functional 2 t min to t max ?40 +125 c temperature sensor accuracy 2 c digital filter response (sinc3) group delay see the src group delay section settling time see the settling time section pass band ?0.1 db see the src bandwidth section ?3 db see the src bandwidth section decimation rate high resolution mode 128 4095.99 low power mode 64 4095.99 clock source frequency high resolution mode 0.655 8.192 mhz low power mode 1.3 4.096 mhz duty cycle 45:55 50:50 55:45 % - adc speed and performance resolution 24 bits output data rate (odr) high resolution mode 16 ksps low power mode 8 ksps no missing codes 24 bits ac accuracy dynamic range shorted inputs, pga gain = 1 16 ksps high resolution mode 108 db 4 ksps high resolution mode 116 db low power mode 106 db 1 ksps low power mode 116 db thd ?0.5 dbfs, high resolution mode ?109 db ?0.5 dbfs, low power mode ?105 db sinad f in = 60 hz 106 db sfdr high resolution mode, 16 ksps, pga gain = 1 132 db intermodulation distortion (imd) f a = 50 hz, f b = 51 hz, high resolution mode ?125 db f a = 50 hz, f b = 51 hz, low power mode ?105 db dc power supply rejection avdd1x = 3.3 v ?90 db dc common-mode rejection ratio 80 db crosstalk ?120 db
data sheet AD7779 rev. 0 | page 7 of 97 parameter test conditions/comments min typ max unit dc accuracy inl endpoint method, pga gain = 1 7 15 ppm of fsr other pga gains 3 15 ppm of fsr offset error 40 125 v offset error drift 0.5 v/c vs. time ?2 v/ 1000 hrs offset matching 25 v gain error 0.1 % fs gain drift vs. temperature pga gain = 1 45 ppm/c gain matching 0.1 % sar adc speed and performance resolution 12 bits analog input range avss4 + 0.1 avdd4 ? 0.1 v analog input common-mode range avss4 + 0.1 (avdd4 + avss4)/2 avdd4 ? 0.1 v analog input leakage current 5 na throughput 256 ksps dc accuracy differential mode inl 1.5 lsb dnl no missing codes (12-bit) ?0.99 +1 lsb offset 1 lsb gain 12 lsb ac performance snr 1 khz 66 db thd 1 khz ?81 db vcm pin output (avdd1x + avssx)/2 v load current, i l 1 ma load regulation, ?v out /?i l 12 mv/ma short-circuit current 5 ma logic inputs input high voltage, v ih 0.7 iovdd v input low voltage, v il 0.4 v hysteresis 0.1 v input currents ?10 +10 a logic outputs 3 output high voltage, v oh iovdd 3 v, i source = 1 ma 0.8 iovdd v 2.3 iovdd < 3 v, i source = 500 a 0.8 iovdd v iovdd < 2.3 v, i source = 200 a 0.8 iovdd v output low voltage, v ol iovdd 3 v, i sink = 2 ma 0.4 v 2.3 iovdd < 3 v, i sink = 1 ma 0.4 v iovdd < 2.3 v, i sink = 100 a 0.4 v leakage current floating state ?10 +10 a output capacitance floating state 10 pf - adc data output coding twos complement sar adc data output coding binary
AD7779 data sheet rev. 0 | page 8 of 97 parameter test conditions/comments min typ max unit power supplies all - channels enabled avdd1x C avssx 3.0 3.6 v i avdd1x 4, 5 reference buffer pre-q, vcm enabled, internal reference enabled high resolution mode 17 22.7 ma low power mode 4.5 6.1 ma reference buffer enabled, vcm enabled, internal reference enabled high resolution mode 19 25.5 ma low power mode 5 6.8 ma reference buffer disabled, vcm disabled, internal reference disabled high resolution mode 13 17.8 ma low power mode 3.5 4.8 ma avdd2x C avssx 2.2 3.6 v i avdd2x high resolution mode 9 9.45 ma low power mode 3.5 3.7 ma avdd4 C avssx avdd1x C 0.3 avdd1x v i avdd4 sar enabled 1.7 2 ma sar disabled 1 10 a avssxv ? dgnd ?1.8 0 v iovdd ? dgnd 1.8 3.6 v i iovdd high resolution mode 8 10.7 ma low power mode 3 4.4 ma power dissipation 6 internal buffers bypassed, internal reference disabled, internal oscillator disabled, sar disabled high resolution mode 16 ksps 86 133 mw low power mode 4 ksps 27 44 mw power-down all adcs disabled 530 w 1 avssx is used to refer to the following pins: avss1a, avss1b, avss2b, and avss2a. this term is used throughout the data sheet. 2 at temperatures higher than 105c, the devi ce can be operated normally, though slig ht degradation on the maximum/minimum speci fications is expected because these specifications are only guaranteed up to 105c. see the typical performance ch aracteristics section for plots showing the typical performance of the device at high temperatures. 3 the sdo pin and the doutx pin are confi gured in the default mode of strength. 4 avdd1x = 3.3 v, avssx = gnd = ground, iovdd = 1.8 v, cmos clock. 5 disabling either the vcm pin or the internal reference re sults in a 40 a typical current consumption reduction. 6 power dissipation is calculated us ing the maximum supply voltage, 3.6 v.
data sheet AD7779 rev. 0 | page 9 of 97 doutx timing characterististics avdd1x/avssx = 1.65 v, 3.3 v/agnd, avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v internal/external, mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 2. parameter description 1 test conditions/comments min typ max unit t 1 mclk frequency 50:50 0.655 8.192 mhz t 2 mclk low time 60 ns t 3 mclk high time 60 ns t 4 dclkx high time mclk/2 122 ns t 5 dclkx low time mclk/2 122 ns t 6 mclk falling edge to dclk rising edge 15 ns t 7 mclk falling edge to dclk falling edge 15 ns t 8 dclkx rising edge to drdy rising edge 5 ns t 9 dclkx rising edge to drdy falling edge 5 ns t 10 doutx setup time 20 ns t 11 doutx hold time 20 ns 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage level of (v il + v ih )/2. mclk dclk drdy lsb msb msb ? 1 lsb + 1 lsb doutx t 2 t 4 t 5 t 6 t 7 t 10 t 11 t 8 t 9 t 1 t 3 13295-002 figure 2. data interface timing diagram
AD7779 data sheet rev. 0 | page 10 of 97 spi timing characterististics avdd1x/avssx = 1.65 v, 3.3 v/agnd, avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v (internal/external), mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 3. parameter description 1 test conditions/comments min typ max unit t 12 sclk period 50:50 30 mhz t 13 sclk low time 7 ns t 14 sclk high time 7 ns t 15 sclk rising edge to cs falling edge 10 ns t 16 cs falling edge to sclk rising edge 10 ns t 17 sclk rising edge to cs rising edge 10 ns t 18 cs rising edge to sclk rising edge 10 ns t 19 minimum cs high time 10 ns t 20 sdi setup time 5 ns t 21 sdi hold time 5 ns t 22a cs falling edge to sdo enable (spi = mode 0) 30 ns t 22b sclk falling edge to sdo enable (spi = mode 1) 49 ns t 23 sdo setup time 10 ns t 24 sdo hold time 10 ns t 25 cs rising edge to sdo disable 30 ns 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage level of (v il + v ih )/2. cs sclk msb msb ? 1 lsb + 1 lsb sdi msb msb ? 1 lsb + 1 lsb sdo t 15 t 16 t 13 t 14 t 20 t 22a t 21 t 24 t 23 t 22b t 12 t 19 t 17 t 18 t 25 13295-003 figure 3. spi control interface timing diagram
data sheet AD7779 rev. 0 | page 11 of 97 synchronization pins and re set timing characteristics avdd1x/avssx = 1.65 v, 3.3 v/agnd, avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v (internal/external), mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 4. parameter description 1 test conditions/comments min typ max unit t 26 start setup time 10 ns t 27 start hold time mclk ns t 28 mclk falling edge to sync_out falling edge mclk ns t 29 sync_in setup time 10 ns t 30 sync_in hold time mclk ns t init_ sync_in sync_in rising edge to first drdy 16 ksps, hp mode 145 s t init_ reset reset rising edge to first drdy 16 ksps, hp mode 225 s t 31 reset hold time 2 mclk ns t power_up start time t power_up is not shown in figure 4 2 ms 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage level of (v il + v ih )/2. mclk start sync_out sync_in drdy reset t 26 t 27 t 28 t 29 t init_sync_in t 31 t init_reset t 30 13295-004 figure 4. synchronization pins and reset control interface timing diagram
AD7779 data sheet rev. 0 | page 12 of 97 sar adc timing characterististics avdd1x/avssx = 1.65 v, 3.3 v/agnd, avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v (internal/external), mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 5. parameter description 1 min typ max unit t 32 conversion time 1 3.4 s t 33 acquisition time 2 500 ns t 34 delay time 50 ns t 35 throughput data 256 ksps 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage level of (v il + v ih )/2. 2 direct mode enabled. if deglitch mode is enabled, add 1.5/mclk. cs convst_sar t 33 t 32 t 35 t 34 13295-005 figure 5. sar adc timing diagram gpio src update timing characterististics avdd1x/avssx = 1.65 v, 3.3 v/agnd, avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0v, refx+/refx? = 2.5 v (internal/external), mclk = 8192 khz; all specifications t min to t max , unless otherwise noted. table 6. parameter description 1 min typ max unit t 36 gpio2 setup time 10 ns gpio2 hold time t 37 high resolution mode mclk ns t 37 low power mode 2 mclk t 38 mclk rising edge to gpio1 rising edge time 20 ns t 39 gpio0 setup time 5 ns t 40 gpio0 hold time mclk ns 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage level of (v il + v ih )/2. mclk gpio2 gpio1 gpio0 t 36 t 37 t 38 t 39 t 40 13295-006 figure 6. gpios for src update timing diagram
data sheet AD7779 rev. 0 | page 13 of 97 absolute maximum ratings table 7. parameter rating any supply pin to avssx ?0.3 v to +3.96 v avssx to dgnd ?1.98 v to +0.3 v aregxcap to avssx ?0.3 v to +1.98 v dregcap to dgnd ?0.3 v to +1.98 v iovdd to dgnd ?0.3 v to +3.96 v iovdd to avssx ?0.3 v to +5.94 v avdd4 to avssx avdd1x ? 0.3 v to 3.96 v analog input voltage avssx ? 0.3 v to avdd1x + 0.3 v or 3.96 v (whichever is less) refx input voltage avssx ? 0.3 v to avdd1x + 0.3 v or 3.96 v (whichever is less) auxain avssx ? 0.3 v to avdd4 + 0.1 v or 3.96v (whichever is less) digital input voltage to dgnd dgnd ? 0.3 v to iovdd + 0.3 v or 3.96 v (whichever is less) digital output voltage to dgnd dgnd ? 0.3 v to iovdd + 0.3 v or 3.96 v (whichever is less) xtal1 to dgnd dgnd ? 0.3 v to dregcap + 0.3 v or 1.98 v (whichever is less) ainx, auxain, and digital input current 10 ma operating temperature range ?40c to +125c junction temperature, t j maximum 150c storage temperature range ?65c to +150c reflow soldering 260c esd 2 kv field induced charged device model (ficdm) 500 v stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. close attention to pcb thermal design is required. table 8. thermal resistance package type 1 ja jb jt jb unit 64-lead lfcsp no thermal vias 1 30.43 n/a 2 0.13 6.59 c/w 49 thermal vias 1 22.62 3.17 0.09 3.19 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal test board. see jedec jesd51. 2 n/a means not applicable. esd caution
AD7779 data sheet rev. 0 | page 14 of 97 pin configuration and function descriptions 13295-007 AD7779 top view (not to scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 convst_sar alert/cs dclk2/sclk dclk1/sdi dclk0/sdo dgnd dregcap iovdd dout3 dout2 dout1 dout0 dclk drdy xtal1 xtal2/mclk 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 auxain? auxain+ avdd4 avss4 avss2a areg1cap avdd2 a vcm clk_sel format0 format1 avss3 avdd2b areg2cap avss2b ref_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ain0? ain0+ ain1? ain1+ avss1a avdd1 a ref1? ref1+ ain2? ain2+ ain3? ain3+ mode0/gpio0 mode1/gpio1 mode2/gpio2 mode3/alert notes 1. exposed pad. connect the exposed pad to avssx. ain4? ain4+ ain5? ain5+ avss1b avdd1b ref2? ref2+ ain6? ain6+ ain7? ain7+ reset sync_in sync_out start 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 figure 7. pin configuration table 9. pin function descriptions pin no. mnemonic type direction description 1 ain0? analog input input analog input channel 0, negative. 2 ain0+ analog input input analog input channel 0, positive. 3 ain1? analog input input analog input channel 1, negative. 4 ain1+ analog input input analog input channel 1, positive. 5 avss1a supply supply negative front-end analog supply for channel 0 to channel 3, typical at ?1.65 v (dual supply) and agnd (single supply). connect all the avssx pins to the same potential. 6 avdd1a supply supply positive front-end analog supply for channel 0 to channel 3, typical at avssx + 3.3 v. connect this pin to avdd1b. 7 ref1 ? reference input negative reference input 1 for channel 0 to channel 3, typical at avssx. connect all the refx ? pins to the same potential. 8 ref1+ reference input positive reference input 1 for channel 0 to channel 3, typical at ref1 ? + 2.5 v. 9 ain2 ? analog input input analog input channel 2, negative. 10 ain2+ analog input input analog input channel 2, positive. 11 ain3 ? analog input input analog input channel 3, negative. 12 ain3+ analog input input analog input channel 3, positive. 13 mode0/gpio0 digital i/o i/o mode 0 input pin in pin control mode (mode0). see table 18 for more details. configurable general-purpose input/output 0 in spi control mode (gpio0). if not in use, connect this pin to dgnd or iovdd. 14 mode1/gpio1 digital i/o i/o mode 1 input pin in pin control mode (mode1). see table 18 for more details. configurable general-purpose input/output 1 in spi control mode (gpio1). if not in use, connect this pin to dgnd or iovdd. 15 mode2/gpio2 digital i/o i/o mode 2 input pin in pin control mode (mode2). see table 18 for more details. configurable general-purpose input/output 2 in spi control mode (gpio2). if not in use, connect this pin to dgnd or iovdd. 16 mode3/alert digital i/o i/o mode 3 input pin in pin control mode (mode3). see table 18 for more details. alert output pin in spi control mode (alert). 17 convst_sar digital input input - output interface selection pin in pin control mode. see table 17 for more details. this pin also functions as the start for the sar conversion in spi control mode.
data sheet AD7779 rev. 0 | page 15 of 97 pin no. mnemonic type direction description 18 alert/cs digital input input alert output pin in pin control mode (alert). chip s elect pin in spi control mode (cs ). 19 dclk 2/sclk digital input input d clk frequency selection pin 2 in pin control mode (dclk2). see table 19 for more details. spi cl ock in spi control mode (sclk). 20 dclk 1/sdi digital input input d clk frequency selection pin 1 in pin control mode (dclk1). see table 19 for more details. spi da ta input in spi control mode (sdi). connect this pin to dgnd if the device is configured in pin control mode with the spi as the data output interface. 21 dcl k0/sdo digital output output d clk frequency selection pin 0 in pin control mode (dclk0). see table 19 for more details. spi da ta output in spi control mode (sdo). 22 dgnd supp ly supply digital ground. 23 dregcap supply output digital ldo output. deco uple this pin to dgnd with a 1 f capacitor. 24 iovdd supply supply d igital levels input/output and digital ldo (dldo) supply from 1.8 v to 3.6 v. iovdd must not be lower than dregcap. 25 d out3 digital output i/o d ata output pin 3. if the device is co nfigured in daisy-chain mode, this pin acts as an input pin. see the daisy-chain mode section for more details. 26 d out2 digital output i/o d ata output pin 2. if the device is co nfigured in daisy-chain mode, this pin acts as an input pin. see the daisy-chain mode section for more details. 27 dout1 digital output output data output pin 1. 28 dout0 digital output output data output pin 0. 29 dclk digital output output data output cloc k. 30 drdy digital output output data output ready pin. 31 x tal 1 clock input cr ystal 1 input connection. if cmos is used as a clock source, tie this pin to dgnd. see table 16 for more details. 32 xtal2/mclk clock input crystal 2 input connection (xtal2). see table 16 for more details. cmos clock (mclk ). see table 16 for more details. 33 start digital input input synchronization pulse. this pin is used to synchronize internally an external start asynchronous pulse with mclk. the synchronize signal is shift out by the sync_out pin. if not in use, tie this pin to dgnd. see the phase adjustment section and the digital reset and synchronization pins section for more details. 34 sync_out digital output input synchronization signal. this pin gene rates a synchronous pulse generated and driven by hardware (via the start pin) or by software (general_user_ config_2, bit 0). if this pin is in use, it must be wired to the sync_in pin. see the phase adjustment and the digital reset and synchronization pins section for more details. 35 sync_in digital input input reset for the internal digital block and synchronize for multiple devices. see the digital reset and sy nchronization pins section for more details. 36 reset digital input input asynchronous reset pin. this pin resets all registers to their default value. it is recommended to generate a pulse on this pin after the device is powered up because a slow slew rate in the supplies may generate an incorrect initialization in the digital block. 37 ain7+ analog input input analog input channel 7, positive. 38 ain7? analog input input analog input channel 7, negative. 39 ain6+ analog input input analog input channel 6, positive. 40 ain6? analog input input analog input channel 6, negative. 41 ref2+ reference input positive reference input 2 for channel 4 to channel 7, typical at ref2? + 2.5 v. 42 re f2? reference input n egative reference input 2 for channel 4 to channel 7, typical at avssx. connect all the refx? pins to the same potential. 43 a vdd1b supply supply p ositive front-end analog supply for ch annel 4 to channel 7. connect this pin to avdd1a. 4 4 a vss1b supply supply n egative front-end analog supply for channel 4 to channel 7, typical at ?1.65 v (dual supply) or agnd (single supply). connect all the avssx pins together. 45 ain5+ analog input input analog input channel 5, positive. 46 ain5? analog input input analog input channel 5, negative. 47 ain4+ analog input input analog input channel 4, positive. 48 ain4? analog input input analog input channel 4, negative.
AD7779 data sheet rev. 0 | page 16 of 97 pin no. mnemonic type direction description 49 ref_out reference output 2.5 v reference output. connect a 100 nf capacitor on this pin if using the internal reference. 50 avss2b supply supply negative analog supply. connect all the avssx pins together. 51 areg2cap supply output analog ldo output 2. decouple this pin to avss2b with a 1 f capacitor. 52 avdd2b supply supply positive analog supply. connect this pin to avdd2a. 53 avss3 supply supply negative analog ground. connect all the avssx pins together. 54 format1 digital input input output data frame 1. see table 17 for more details. 55 format0 digital input input output data frame 0. see table 17 for more details. 56 clk_sel digital input input select clock source. see table 16 for more details. 57 vcm analog output output common-mode voltage output, typical at (avdd1 + avssx)/2. 58 avdd2a supply input analog supply from 2.2 v to 3.6 v. avss2x must not be lower than aregxcap. connect this pin to avdd2b. 59 areg1cap supply output analog ldo output 1. decouple this pin to avss with a 1 f capacitor. 60 avss2a supply input negative analog supply. connect all the avssx pins together. 61 avss4 supply supply negative sar analog supply and reference. connect all avssx pins together. 62 avdd4 supply supply positive sar analog supply and reference source. 63 auxain+ analog input input positive sar analog input channel. 64 auxain? analog input input negative sar analog input channel. epad supply input exposed pad. connect the exposed pad to avssx.
data sheet AD7779 rev. 0 | page 17 of 97 typical performance characteristics ?8 ?6 ?4 ?2 0 2 4 8 6 ?2.48 ?2.12 ?1.77 ?1.41 ?1.06 ?0.70 ?0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 inl (ppm) input voltage (v) gain = 1 temperature = 25c differential input signal v ref =2.5v v cm = (avdd1x + avssx) 2 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13295-016 figure 8. inl vs. input voltage and channel at 8 ksps, high resolution mode, avssx (v cm is the voltage on the vcm pin) ?6 ?4 ?2 0 2 4 6 ?2.48 ?2.12 ?1.77 ?1.41 ?1.06 ?0.70 ?0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 inl (ppm) input voltage (v) gain = 1 gain = 2 gain = 4 gain = 8 temperature = 25c v ref =2.5v differential v in gain v cm = (avdd1x + avssx) 2 13295-009 figure 9. inl vs. input voltage and pga gain at 8 ksps, high resolution mode, avssx ?6 ?4 ?2 0 2 4 6 ?2.48 ?2.12 ?1.77 ?1.41 ?1.06 ?0.70 ?0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 inl (ppm) input voltage (v) t a = ?40c t a = +25c t a = +105c t a = +125c gain = 1 differential input signal v ref = 2.5v v cm = (avdd1x + avssx) 2 13295-010 figure 10. inl vs. input voltag e and temperature at 8 ksps, high resolution mode, avssx ?8 ?6 ?4 ?2 0 2 4 8 6 ?2.48 ?2.12 ?1.77 ?1.41 ?1.06 ?0.70 ?0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 inl (ppm) input voltage (v) gain = 1 temperature = 25c differential input signal v ref =2.5v v cm = (avdd1x + avssx) 2 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13295-019 figure 11. inl vs. input voltage and channel at 2 ksps, low power mode, avssx ?8 ?6 ?4 ?2 0 2 4 8 6 ?2.48 ?2.12 ?1.77 ?1.41 ?1.06 ?0.70 ?0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 inl (ppm) input voltage (v) differential v in gain temperature = 25c v ref =2.5v v cm = (avdd1x + avssx) 2 gain = 1 gain = 2 gain = 4 gain = 8 13295-012 figure 12. inl vs. input voltage and pga gain at 2 ksps, low power mode, avssx ?10 ?8 ?6 ?4 ?2 0 2 4 10 8 6 ?2.48 ?2.12 ?1.77 ?1.41 ?1.06 ?0.70 ?0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 inl (ppm) input voltage (v) gain = 1 differential input signal v ref =2.5v v cm = (avdd1x + avssx) 2 t a = ?40c t a = +25c t a = +105c t a = +125c 13295-013 figure 13. inl vs. input voltage and temperature at 2 ksps, high resolution mode, avssx
AD7779 data sheet rev. 0 | page 18 of 97 inl (ppm) gain = 1 temperature = 25c differential input signal v cm = (avdd1x + avssx) 2 ?3.6 ?2.6 ?1.6 ?0.6 0.4 1.4 2.4 3.4 input voltage (v) ?15 ?10 ?5 0 5 10 15 v ref = 3.3v v ref = 3.0v v ref = 2.5v v ref = 2.0v v ref = 1.5v v ref = 1.0v 13295-014 figure 14. inl vs. input voltage and reference voltage (v ref ) at 8 ksps, high resolution mode, avssx ?10 ?8 ?6 ?4 ?2 0 2 4 10 8 6 ?2.48 ?2.12 ?1.77 ?1.41 ?1.06 ?0.70 ?0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 inl (ppm) input voltage (v) v cm = 1.35v v cm = 1.95v v cm = 1.65v gain = 1 temperature = 25c differential input signal v ref =2.5v 13295-015 figure 15. inl vs. input voltage and v cm at 8 ksps, high resolution mode 0 200 400 600 800 1000 1200 1400 1600 1800 2000 8388300 8388314 8388328 8388342 8388356 8388370 8388384 8388398 8388412 8388426 8388440 8388454 8388468 8388482 8388496 8388510 8388524 8388538 8388552 8388566 8388580 8388594 sample count adc code v ref =2.5v temperature = 25c v cm = (avdd1x + avssx) 2 gain = 1 gain = 2 gain = 4 gain = 8 13295-022 figure 16. noise histogram at 8 ksps, high resolution mode inl (ppm) gain = 1 temperature = 25c differential input signal v cm = (avdd1x + avssx) 2 ?3.6 ?2.6 ?1.6 ?0.6 0.4 1.4 2.4 3.4 input voltage (v) ?15 ?10 ?5 0 5 10 15 v ref = 3.3v v ref = 3.0v v ref = 2.5v v ref = 2.0v v ref = 1.5v v ref = 1.0v 13295-017 figure 17. inl vs. input voltage and reference voltage (v ref ) at 2 ksps, low power mode, avssx ?10 ?8 ?6 ?4 ?2 0 2 4 10 8 6 ?2.48 ?2.12 ?1.77 ?1.41 ?1.06 ?0.70 ?0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 inl (ppm) input voltage (v) v cm = 1.35v v cm = 1.95v v cm = 1.65v gain = 1 temperature = 25c differential input signal v ref =2.5v 13295-018 figure 18. inl vs. input voltage and v cm at 2 ksps, low power mode 0 200 400 600 800 1000 1200 1400 1600 1800 2000 sample code gain = 1 gain = 2 gain = 4 gain = 8 13295-225 8388100 8388142 8388184 8388226 8388268 8388310 8388352 8388394 8388436 8388478 8388520 8388562 8388604 8388646 8388688 8388730 8388772 adc code v ref =2.5v temperature = 25c v cm = (avdd1x + avssx) 2 figure 19. noise histogram at 2 ksps, low power mode
data sheet AD7779 rev. 0 | page 19 of 97 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?40 25 105 125 noise (v rms) temperature (c) gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v v cm = (avdd1x + avssx) 2 13295-026 figure 20. noise vs. temperature at 8 ksps, high resolution mode 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 596720 1057040 1517360 1977680 2438000 2898320 3358640 3818960 4279280 4739600 5199920 5660240 6120560 6580880 7041200 7501520 7961840 noise (v rms) clock frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 13295-032 v ref =2.5v temperature = 25c decimation = 256 v cm =(avdd1x+avssx) 2 figure 21. noise vs. clock frequency, high resolution mode, decimation = 256 100 2000 4000 8000 1600 noise (nv/ 13295-097 0 20 40 60 80 100 120 figure 22. noise vs. odr, high resolution mode 0 1 2 3 4 5 6 7 8 9 10 ?40 25 105 125 noise (v rms) temperature (c) gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v v cm = (avdd1x + avssx) 2 13295-029 figure 23. noise vs temperature at 2 ksps, low power mode 0 1 2 3 4 5 6 298360 528520 758680 988840 1219000 1449160 1679320 1909480 2139640 2369800 2599960 2830120 3060280 3290440 3520600 3750760 3980920 noise (v rms) clock frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 13295-035 v ref =2.5v temperature = 25c decimation = 256 v cm =(avdd1x+avssx) 2 figure 24. noise vs. clock frequency at 2 ksps, low power mode, decimation = 256 0 50 100 150 200 250 300 350 400 500 1000 2000 4000 8000 noise (nv/ hz) odr (hz) gain = 1 gain = 2 gain = 4 gain = 8 13295-098 figure 25. noise vs. odr, low power mode
AD7779 data sheet rev. 0 | page 20 of 97 ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 58.593750 117.187500 175.781250 234.375000 292.968750 351.562500 410.156250 468.750000 527.343750 585.937500 644.531250 703.125000 761.718750 820.312500 878.906250 937.500000 996.093750 amplitude (db) frequency (hz) v ref =2.5v temperature = 25c differential input = ?0.5dbfs v cm = (avdd1x + avssx) 2 input frequency = 50hz 16384 samples 16ksps gain = 1 gain = 2 gain = 4 gain = 8 13295-020 figure 26. fft plot at 16 ksps, high resolution mode, input frequency (f in ) = 50 hz, avssx (this plot is a close up perspective of the original data) ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 277.343750 554.687500 832.031250 1109.37500 1386.71875 1664.06250 1941.40625 2218.75000 2496.09375 2773.43750 3050.78125 3328.12500 3605.46875 3882.81250 4160.15625 4437.50000 4714.84375 4992.10875 5269.53125 5546.87500 5824.21875 6101.56250 6378.90625 6656.25000 6933.59375 7210.93750 7488.28125 7765.62500 amplitude (db) frequency (hz) v ref =2.5v temperature = 25c differential input = ?0.5dbfs v cm = (avdd1x + avssx) 2 input frequency = 1khz 16384 samples 16ksps gain = 1 gain = 2 gain = 4 gain = 8 13295-021 figure 27. fft plot, high resolution mode, input frequency (f in ) = 1 khz, avssx ?135 ?130 ?125 ?120 ?115 ?110 ?105 ? 100 10 90 170 250 330 410 490 570 650 730 810 890 970 1355 1923 2491 3059 3627 4266 4905 5544 6112 6751 7390 7958 thd (db) input frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 v in = ?0.5dbfs v ref =2.5v temperature = 25c 13295-033 figure 28. thd vs. input frequency at 8 ksps, high resolution mode ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 31.25 62.50 93.75 125.00 156.25 187.50 218.75 250.00 281.25 312.50 343.75 375.00 406.25 437.50 468.75 500.00 531.25 562.50 593.75 625.00 656.25 687.5 718.75 750.00 781.25 812.50 843.75 875.00 906.25 937.50 968.75 amplitude (db) frequency (hz) v ref =2.5v temperature = 25c differential input = ?0.5dbfs v cm = (avdd1x + avssx) 2 input frequency = 50hz 8192 samples 4ksps gain = 1 gain = 2 gain = 4 gain = 8 13295-023 figure 29. fft plot, low power mode, input frequency (f in ) = 50 hz, 8192 samples, avssx (this plot is a close up perspective of the original data) ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 66.40625 132.81250 199.21875 265.62500 332.03125 398.43750 464.84375 531.25000 597.65625 664.06250 730.46875 796.87500 863.28125 929.68750 996.09375 1062.50000 1128.90625 1195.31250 1261.71875 1328.12500 1394.53125 1460.93750 1527.34375 1593.75000 1660.15625 1726.56250 1792.96875 1859.37500 1925.78125 1992.18750 amplitude (db) frequency (hz) v ref =2.5v temperature = 25c differential input = ?0.5dbfs input frequency = 1khz 8192 samples 4ksps gain = 1 gain = 2 gain = 4 gain = 8 13295-024 v cm = (avdd1x + avssx) 2 figure 30. fft plot, low power mode, input frequency (f in ) = 1 khz, 8192 samples, avssx ?135 ?130 ?125 ?120 ?115 ?110 ?105 ? 100 10 70 130 190 250 310 370 460 530 590 650 710 770 840 900 960 1066 1198 1352 1484 1616 1748 1880 2012 thd (db) input frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v v in = ?0.5dbfs temperature = 25c 13295-036 figure 31. thd vs. input freque ncy at 2 ksps, low power mode
data sheet AD7779 rev. 0 | page 21 of 97 ?140 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ? 100 0.172 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 4.644 thd (db) input voltage (v) input frequency = 50hz v ref =2.5v temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 13295-034 figure 32. thd vs. input voltage at 2 ksps, high resolution mode (input frequency = 50 hz) ?125 ?120 ?115 ?110 ?105 ?100 ?95 ? 90 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 thd (db) reference voltage (v) gain = 1 gain = 2 gain = 4 gain = 8 input frequency = 50hz temperature = 25c input voltage = v ref 13295-038 figure 33. thd vs. reference voltage at 8 ksps, high resolution mode (input frequency = 50 hz) ?120 -118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 ?102 ? 100 655000 1043250 1564770 2086290 2607810 3129330 3650850 4172370 4693890 5215410 5736930 6258450 6779970 7301490 7823010 thd (db) mclk frequency (hz) v ref =2.5v input voltage = ?0.5dbfs input frequency = 50hz temperature = 25c decimation = 256 gain = 1 gain = 2 gain = 4 gain = 8 13295-039 figure 34. thd vs. mclk frequency, high resolution mode, input frequency (f in ) = 50 hz, decimation = 256 ?140 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ? 100 0.172 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 4.644 thd (db) input voltage (v) input frequency = 50hz v ref =2.5v temperature = 25c gain = 1 gain = 2 gain = 4 gain = 8 13295-037 figure 35. thd vs. input voltage at 500 sps, low power mode ?125 ?120 ?115 ?110 ?105 ?100 ?95 ? 90 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 thd (db) reference voltage (v) gain = 1 gain = 2 gain = 4 gain = 8 input frequency = 50hz temperature = 25c input voltage = 5v p-p 13295-041 figure 36. thd vs. reference voltage at 2 ksps, low power mode (input frequency = 50 hz) ?120 ?118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 ?102 ? 100 235840 665920 1096000 1216000 1336000 1456000 1576000 1696000 1816000 1936000 2056000 2176000 2296000 2416000 2536000 2656000 2776000 2896000 3016000 3136000 3256000 3376000 3496000 3616000 3736000 3856000 3976000 4096000 thd (db) frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 decimation = 256 input frequency = 50hz v ref =2.5v input voltage = 5v p-p temperature = 25c 13295-042 figure 37. thd vs. mclk frequency, low power mode, input frequency (f in ) = 50 hz, decimation = 256
AD7779 data sheet rev. 0 | page 22 of 97 85 90 95 100 105 110 115 120 125 12481 6 snr (db) odr (khz) gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v v in =0dbfs temperature = 25c 13295-040 figure 38. snr vs. odr at 8 ksps, high resolution mode (avddx = 3.6 v, av ss = 1.8 v, iovdd = 3.6 v) 60 70 80 90 100 110 120 dynamic range (db) pga gain 8000 gain = 1 gain = 2 gain = 4 gain = 8 13295-089 figure 39. dynamic range vs. pga gain, high resolution mode, odr = 8 ksps ?60 ?50 ?40 ?30 ?20 ?10 0 1248 offset error (v) pga gain ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13295-044 avdd1x = 3.3v v ref =2.5v temperature = 25c v in =0v figure 40. offset error vs. pga gain, high resolution mode, avdd1x = 3.3 v 85 90 95 100 105 110 115 120 125 0 . 51248 snr (db) odr (khz) gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v temperature = 25c input voltage = 5v p-p input frequency = 50hz 13295-043 v in = 0dbfs figure 41. snr vs. odr at 2 ksps, low power mode (avddx = 3.6 v, av ss = 1.8 v, iovdd = 3.6 v) 60 70 80 90 100 110 120 dynamic range (db) pga gain 2000 gain = 1 gain = 2 gain = 4 gain = 8 13295-090 figure 42. dynamic range vs. pga gain, low power mode, odr = 2 ksps ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1248 offset error (v) pga gain ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 v ref =2.5v temperature = 25c v in =0v 13295-047 avdd1x = 3.3v figure 43. offset error vs. pga gain, low power mode, avdd1x = 3.3 v
data sheet AD7779 rev. 0 | page 23 of 97 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 3.0 3.3 3.6 offset error (v) supply setting gain = 1 gain = 2 gain = 4 gain = 8 v ref =2.5v v in =0v temperature = 25c 13295-051 figure 44. offset error vs. supply setting, high resolution mode offset drift (v) temperature (c) 13295-045 ?40 ?30 ?20 ?10 0 10 20 30 ?37.624 ?30.430 ?22.232 ?13.506 0.073 9.272 18.298 26.714 35.461 45.142 54.035 62.669 70.920 78.593 87.104 95.349 105.439 115.991 124.589 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 avdd1x = 3.3v figure 45. offset drift vs. temperature, avdd1x = 3.3 v ?0.043 ?0.035 ?0.026 ?0.017 ?0.008 0 0.008 0.017 3.0 3.3 3.6 gain error (%) avdd1x supp ly (v) temperature = 25c gain = 1 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13295-056 figure 46. gain error vs. avdd1x supply, high resolution mode offset error (v) ?40 ?35 ?45 ?30 ?25 ?20 ?15 ?10 ?5 0 3.0 3.3 3.6 supply setting temperature = 25c v in = 0v v ref = 2.5v gain = 1 gain = 2 gain = 4 gain = 8 13295-054 figure 47. offset error vs. supply setting, low power mode ?15 ?10 ?5 0 5 10 15 20 25 30 35 0 500 1000 gain error drift (ppm) time (hours) 13295-058 figure 48. gain error drift vs. time 3.0 3.3 3.6 avdd1x supply (v) temperature = 25c gain = 1 gain error (%) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13295-059 ?0.043 ?0.035 ?0.026 ?0.017 ?0.008 0 0.008 0.017 figure 49. gain error vs. avdd1x supply, low power mode
AD7779 data sheet rev. 0 | page 24 of 97 ?40 25 105 125 gain error (%) temperature (c) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13295-057 avdd1x = 3.3v ?0.400 ?0.035 ?0.029 ?0.023 ?0.017 ?0.011 ?0.005 0 0.005 0.011 0.017 figure 50. gain error vs temperature, high resolution mode, avdd1x = 3.3 v 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 1248 gain error (%) pga gain temperature = 25c high resolution low power 13295-052 avdd1x = 3.3v figure 51. channel gain mismatch, high resolution mode, avdd1x = 3.3 v ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 125 tue (% of input) temperature (c) v ref =2.5v v in =?0.5dbfs gain = 1 13295-082 avdd1x = 3.3v figure 52. total unadjusted error (tue ) (as % of input) vs. temperature, high resolution mode, avdd1x = 3.3 v ?0.400 ?0.035 ?0.029 ?0.023 ?0.017 ?0.011 ?0.005 0 0.005 0.011 0.017 ?40 25 105 125 gain error (%) temperature (c) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13295-060 avdd1x = 3.3v figure 53. gain error vs. temperature, low power mode, avdd1x = 3.3 v ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?40 ?20 0 20 40 60 80 100 120 reference v o ltage drift (mv) temperature (c) unit 1 unit 2 unit 3 unit 4 unit 5 unit 6 unit 7 13295-099 figure 54. internal reference voltage drift ?40 ?30 ?20 ?10 10 0 20 30 40 50 60 70 80 90 100 110 125 temperature (c) ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 tue (% of input) v ref =2.5v v in =?0.5dbfs gain = 1 13295-085 avdd1x = 3.3v figure 55. tue (as % of input) vs. temperature, low power mode, avdd1x = 3.3 v
data sheet AD7779 rev. 0 | page 25 of 97 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 input currfent (na) differential input voltage ((ainx+) ? (ainx?)) ainx+ v cm = 1.95v ainx? v cm = 1.95v ainx+ v cm = 1.35v ainx? v cm = 1.35v v ref = 2.5v v in = 2.5v avdd1 = 3.3v 13295-076 figure 56. input current vs. differential input voltage, high resolution mode ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 4 3 5 ?0.073 ?8.000 ?16.000 ?24.000 ?32.000 ?40.000 9.272 18.298 26.714 35.461 45.142 54.035 62.669 70.920 78.593 87.104 95.349 105.439 115.991 124.589 absolute input current (na) temperature (c) v ref =2.5v v in =2.5v avdd1x = 3.3v ain0+ ain0? ain2+ ain2? 13295-080 figure 57. absolute input current vs. temperature, high resolution mode 0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.5 2.0 differenti a l input current (na) differential input voltage ((ainx+) ? (ainx?)) ?2.0 ?1.5 ?1.0 ?0.5 0.5 1.0 1.5 2.0 ainx+ ? ainx? v cm = 1.95v ainx+ ? ainx? v cm = 1.35v v ref =2.5v v in =2.5v avdd1x = 3.3v 13295-091 figure 58. differential input current vs. differential input voltage, high resolution mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 ? 2.5?2.0?1.5?1.0?0.5 0 0.5 1 1.5 2 2.5 input current (na) v ref =2.5v v in =2.5v avdd1x = 3.3v differential input voltage ((ainx+) ? (ainx?)) ainx+ v cm = 1.95v ainx? v cm = 1.95v ainx+ v cm = 1.35v ainx? v cm = 1.35v 13295-079 figure 59. input current vs. differential input voltage, low power mode ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 ?0.073 ?8.000 ?16.000 ?24.000 ?32.000 ?40.000 9.272 18.298 26.714 35.461 45.142 54.035 62.669 70.920 78.593 87.104 95.349 105.439 115.991 124.589 absolute input current (na) temperature (c) v ref =2.5v v in =2.5v avdd1x = 3.3v ain0+ ain0? ain2+ ain2? 13295-083 figure 60. absolute input current vs. temperature, low power mode ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.5 2.0 differenti a l input current (na) differential input voltage ((ainx+) ? (ainx?)) ainx+ ? ainx? v cm = 1.95v ainx+ ? ainx? v cm = 1.35v 13295-093 figure 61. differential input current vs. differential input voltage, low power mode
AD7779 data sheet rev. 0 | page 26 of 97 ?0.073 ?8.000 ?16.000 ?24.000 ?32.000 ?40.000 9.272 18.298 26.714 35.461 45.142 54.035 62.669 70.920 78.593 87.104 95.349 105.439 115.991 124.589 differenti a l input current (na) temperature (c) ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 v ref =2.5v v in =2.5v avdd1x = 3.3v 0 1 2 3 4 5 6 7 8 9 10 13295-092 figure 62. differential input current vs. temperature, high resolution mode ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 6903.641 13794.282 20684.924 27575.565 34466.206 41356.847 48247.488 55138.130 62028.771 68919.412 75810.053 82700.694 89591.335 96481.977 103372.618 110263.259 117153.900 124044.541 130935.183 137825.824 144756.066 151646.708 158576.950 165507.193 172437.435 179367.678 186297.920 193228.163 cmrr (db) input frequency (hz) gain 1 gain 2 gain 4 gain 8 13.000 13295-062 avdd1x = 3.3v v cm = 1.65v + 100mv p-p figure 63. cmrr vs. input frequency at 8 ksps, high resolution mode, avdd1x = 3.3 v, v cm = 1.65 v + 100 mv p-p ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 380962 761914 1142866 1523818 1904770 2285722 2666674 3047626 3428578 3809530 4190482 4571434 4952386 5333338 5714290 6095242 6476194 6857146 7238098 7619050 8000002 8390478 8790477 9190477 9590477 9990476 ac psrr (db) gain 1 gain 2 gain 4 gain 8 input frequency (hz) 13295-063 temperature = 25c avdd1x = 3.3v + 100mv p-p figure 64. ac psrr vs. input frequency at 8 ksps, high resolution mode, avdd1x = 3.3 v + 100 mv p-p ?0.073 ?8.000 ?16.000 ?24.000 ?32.000 ?40.000 9.272 18.298 26.714 35.461 45.142 54.035 62.669 70.920 78.593 87.104 95.349 105.439 115.991 124.589 0 1 2 3 4 5 6 7 8 differenti a l input current (na) temperature (c) ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 v ref =2.5v v in =2.5v avdd1x = 3.3v 13295-094 figure 65. differential input current vs. temperature, low power mode ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 13.000 8250.088 16487.177 24724.265 32961.353 41198.442 49435.530 57672.618 65909.707 74146.795 82383.883 90620.971 98858.060 107095.148 115332.236 123569.325 131806.413 140043.501 148280.590 156517.678 164754.766 172991.855 181228.943 189466.031 197782.322 cmrr (db) input frequency (hz) 13295-065 gain 1 gain 2 gain 4 gain 8 avdd1x = 3.3v v cm = 1.65v + 100mv p-p figure 66. cmrr vs. input frequency at 2 ksps, low power mode, avdd1x = 3.3 v, v cm = 1.65 v + 100 mv p-p input frequency (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 380962 761914 1142866 1523818 1904770 2285722 2666674 3047626 3428578 3809530 4190482 4571434 4952386 5333338 5714290 6095242 6476194 6857146 7238098 7619050 8000002 8390478 8790477 9190477 9590477 9990476 ac psrr (db) temperature = 25c avdd1x = 3.3v + 100mv p-p gain 1 gain 2 gain 4 gain 8 13295-066 v cm = 1.65v + 100mv p-p figure 67. ac psrr vs. input frequency at 2 ksps, low power mode, avdd1x = 3.3 v + 100 mv p-p
data sheet AD7779 rev. 0 | page 27 of 97 ?120 ?100 ?80 ?60 ?40 ?20 0 25 664 1303 1942 2581 3220 3859 4498 5137 5776 6415 7054 7693 8332 8971 9610 10249 10888 11527 12166 12805 13444 14083 14722 15361 a ttenu a tion (db) frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 13295-086 figure 68. filter profiles at 8 ksps, high resolution mode 13295-064 0 2 4 6 8 10 12 14 16 18 20 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supply current (ma) supply voltage (v) avdd1 avdd2 avdd4 iovdd all channels enabled figure 69. supply current vs. supply voltage at 8 ksps, high resolution mode temperature (c) 0 5 10 15 20 25 ?40 ?20 0 20 40 60 80 100 120 avdd1 avdd2 avdd4 iovdd supply current (ma) 13295-069 all channels enabled figure 70. supply current vs. temperature at 8 ksps, high resolution mode ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 25 344 663 982 1301 1620 1939 2258 2577 2896 3215 3534 3853 4172 4491 4810 5129 5448 5767 6086 6405 6724 7043 7362 7681 a ttenu a tion (db) frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 13295-087 figure 71. filter profiles at 2 ksps, low power mode 0 1 2 3 4 5 6 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supply voltage (v) avdd1 avdd2 avdd4 iovdd supply current (ma) 13295-067 all channels enabled figure 72. supply current vs. supply voltage at 2 ksps, low power mode temperature (c) 0 1 2 3 4 5 6 7 ?40 ?20 0 20 40 60 80 100 120 supply current (ma) avdd1 avdd2 avdd4 iovdd 13295-072 all channels enabled figure 73. supply current vs. temperature at 2 ksps, low power mode
AD7779 data sheet rev. 0 | page 28 of 97 ?800 ?600 ?400 ?200 0 200 400 600 800 ?35.263 ?29.594 ?22.185 ?15.223 ?7.366 ?0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 reference input current (na) temperature (c) ref1? ref1+ ref2? ref2+ 13295-096 figure 74. reference input current vs. temperature, high resolution mode 13295-074 ?10 0 10 20 30 40 50 60 70 80 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 shutdown supply current (a) supply volatge (v) avdd1 avdd2 avdd4 iovdd figure 75. shutdown supply current vs. supply voltage 0 5 10 15 20 25 30 35 40 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 power consumption (mw) supply voltage (v) avdd1 avdd2 avdd4 13295-068 figure 76. power consumption per channel vs. supply voltage at 8 ksps, high resolution mode ?35.263 ?29.594 ?22.185 ?15.223 ?7.366 ?0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 reference input current (na) temperature (c) ref1? ref1+ ref2? ref2+ ?600 ?500 ?400 ?300 ?200 ?100 0 100 200 300 13295-095 figure 77. reference input current vs. temperature, low power mode ?50 0 50 100 150 200 250 ?40 ?20 0 20 40 60 80 100 120 temperature (c) avdd1 avdd2 avdd4 iovdd shutdown supply current (a) 13295-078 figure 78. shutdown supply current vs. temperature 0 2 4 6 8 10 12 14 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 power consumption (mw) supply voltage (v) avdd1 avdd2 avdd4 13295-071 figure 79. power consumption per channel vs. supply voltage at 2 ksps, low power mode
data sheet AD7779 rev. 0 | page 29 of 97 temperature (c) 0 10 20 30 40 50 60 70 80 90 ?40 ?20 0 20 40 60 80 100 120 power dissip a tion (mw) avdd1 avdd2 avdd4 13295-070 figure 80. power dissipation vs. temperature at 8 ksps, high resolution mode temperature (c) 0 5 10 15 20 25 power dissip a tion (mw) ?40 ?20 0 20 40 60 80 100 120 13295-073 avdd1 avdd2 avdd4 figure 81. power dissipation vs. temperature at 2 ksps, low power mode
AD7779 data sheet rev. 0 | page 30 of 97 terminology common-mode rejection ratio (cmrr) cmrr is the ratio of the power in the adc output at full- scale frequency, f, to the power of a 100 mv p-p sine wave applied to the common-mode voltage of v in+ and v in? at frequency, f s . cmrr (db) = 10 log( pf / pf s ) where: pf is the power at frequency, f , in the adc output. pf s is the power at frequency, f s , in the adc output. differential nonlinearity (dnl) error in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. dnl error is often specified in terms of resolution for which no missing codes are guaranteed. integral nonlinearity (inl) error integral noninearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. dynamic range dynamic range is the ratio of the rms value of the full-scale input signal to the rms noise measured for an input. the value for dynamic range is expressed in decibels. channel to channel isolation channel to channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full- scale frequency sweep sine wave signal to all seven nonselected input channels and determining how much that signal is attenuated in the selected channel. the figure is given for worst case scenarios across all eight channels of the AD7779 . intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa and nfb, where m, n = 0,1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to 0. for example, the second-order terms include (fa + fb) and (fa ? fb), and the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the AD7779 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second- order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in decibels. gain error the first transition (from 100 000 to 100 001) occurs at a level ? lsb above nominal negative full scale ( ? 2.49999 v for the 2.5 v range). the last transition (from 011 110 to 011 111) occurs for an analog voltage 1? lsb below the nominal full scale (2.49999 v for the 2.5v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. gain error drift gain error drift is the ratio of the gain error change due to a temperature change of 1c and the full-scale range (2 n ). it is expressed in parts per million. least significant bit (lsb) the least significant bit, or lsb, is the smallest increment that can be represented by a converter. for a fully differential input adc with n bits of resolution, the lsb expressed in volts is lsb (v) = n ref v 2 2 ? lsb ( v in ) = n gain ref pga v 2 2 ? power supply rejection ratio (psrr) variations in power supply affect the full-scale transition but not the linearity of the converter. psrr is the maximum change in the full-scale transition point due to a change in the power supply voltage from the nominal value. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal (including harmonics). total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. offset error offset error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. offset error drift offset error drift is the ratio of the offset error change due to a temperature change of 1c and the full-scale code range (2 n ). it is expressed in v/c.
data sheet AD7779 rev. 0 | page 31 of 97 rms noise and resolution table 10 through table 12 show the dynamic range (dr), rms noise (rti), effective number of bits (enob), and effective resolution (er) of the AD7779 for various output data rates and gain settings. the numbers given are for the bipolar input range with an external 2.5 v reference. these numbers are typical and are generated with a differential input voltage of 0 v when the adc is continuously converting on a single channel. it is important to note that the effective resolution is calculated using the rms noise; 16,384 consecutives samples were used to calculate the rms noise. effective resolution = log2(input range / rms noise ) enob = (dr ? 1.78)/6 high resolution mode table 10. dr (db) and rti (v rms ) for high resolution mode decimation rate output data rate (sps) f ?3db (hz) gain 1 2 4 8 dr rti dr rti dr rti dr rti 128 16000 5029.99 108.28 6.80 105.13 4.80 101 3.95 95.86 3.46 256 8000 2521.99 112.5 4.12 110.21 2.63 106.8 2.01 102 1.72 512 4000 1267.99 116.12 2.70 114.7 1.59 111.6765 1.11 107.61 0.93 1024 2000 640.99 119.5 1.87 118.3 1.07 115.82 0.70 112 0.57 2048 1000 327.49 122.37 1.33 121.55 0.74 119 0.49 115.5 0.38 table 11. enob and er for high resolution mode decimation rate output data rate (sps) f ?3db (hz) gain 1 2 4 8 enob er enob er enob er enob er 128 16000 5029.99 17.75 19.49 17.23 18.99 16.54 18.27 15.68 17.46 256 8000 2521.99 18.46 20.21 18.08 19.86 17.51 19.25 16.71 18.47 512 4000 1267.99 19.06 20.82 18.82 20.58 18.32 20.10 17.64 19.36 1024 2000 640.99 19.62 21.35 19.42 21.16 19.01 20.76 18.37 20.08 2048 1000 327.49 20.1 21.84 19.97 21.69 19.54 21.28 18.96 20.66 low power mode table 12. dr and rti (v rms ) for low power mode decimation rate output data rate (sps) f ?3db (hz) gain 1 2 4 8 dr rti dr rti dr rti dr rti 64 8000 2521.99 100 19.1 96 13.4 92 11.2 87 10.3 128 4000 1267.99 106 8.82 103 6.18 98.5 5.2 94 4.65 256 2000 640.99 112 4.53 108.5 3.03 106 2.32 100.5 2.05 512 1000 327.49 116 2.89 114 1.77 111 1.24 107 1.04 table 13. enob and er for low power mode decimation rate output data rate (sps) f ?3db (hz) gain 1 2 4 8 enob er enob er enob er enob er 64 8000 2521.99 16.37 18.00 15.71 17.51 15.04 16.77 14.21 15.89 128 4000 1267.99 17.37 19.11 16.87 18.63 16.12 17.87 15.37 17.04 256 2000 640.99 18.37 20.07 17.79 19.65 17.37 19.04 16.46 18.22 512 1000 327.49 19.04 20.72 18.71 20.43 18.21 19.94 17.54 19.20
AD7779 data sheet rev. 0 | page 32 of 97 theory of operation the AD7779 is an 8-channel, simultaneously sampling, low noise, 24-bit ? - adc with integrated digital filtering per channel and src. the AD7779 offers two operation modes: high resolution mode, which offers up to 16 ksps, and low power mode, which offers up to 8 ksps. in low power mode, the specifications are guaranteed up to 4 ksps, with performance degradation expected at odrs higher than 4 ksps. the AD7779 employs a ? - conversion technique to convert the analog input signal into an equivalent digital word. the overview of the ? - technique is that the modulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, f clkin . due to the high oversampling rate, this technique spreads the quantization noise from 0 to f clkin /2 (in the case of the AD7779 , f clkin relates to the external clock); therefore, the noise energy contained in the band of interest is reduced (see figure 82). to further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest (see figure 83). the digital filter that follows the modulator removes the large out of band quantization noise (see figure 84). for more information on basic and advanced concepts of ? - adcs, see mt-022 and mt-023 . digital filtering has certain advantages over analog filtering. because digital filtering occurs after the analog-to-digital conversion process, it can remove noise injected during the conversion. analog filtering cannot remove noise injected during conversion. quantization noise f iclk \2 band of interest 13295-100 figure 82. ? -? adc operation, reduction of noise energy contained in the band of interest (linear scale x-axis) f iclk \2 noise shaping band of interest 13295-101 figure 83. ? -? adc operation, majority of noise energy shifted out of the band of interest (linear scale x-axis) f iclk \2 band of interest digital filter cutoff frequency 13295-102 figure 84. ? -? adc operation, removal of noise energy from the band of interest (linear scale x-axis) the ? - adc starts the conversions of the input signal after the supplies generated by the internal ldos become stable. an external signal is not required to generate the conversions. analog inputs the AD7779 can be operated in bipolar or unipolar modes and accepts true differential, pseudo differential, and single-ended input signals, as shown in figure 85 through figure 88. table 14 summarizes the maximum differential input signal and dynamic range for the different input modes. table 14. input signal modes input signal mode pga gain maximum differential signal maximum peak-to-peak signal true differential all gains ( v ref / pga gain ) 2 v ref /pga gain pseudo differential all gains ( v ref / pga gain ) 2 v ref /pga gain single-ended all gains v ref / pga gain v ref /pga gain
data sheet AD7779 rev. 0 | page 33 of 97 bipolar or unipola r true differenti a l avdd1x ? 0.1v ainx+ ainx+ avssx + 0.1v vcm v ref /pga gain 13295-103 figure 85. ? -? adc input signal config uration, true differential bipolar or unipolar pseudo differenti a l avdd1x ? 0.1v ainx+ ainx+ avssx + 0.1v vcm v ref /pga gain 13295-104 figure 86. ? -? adc input signal configuration, pseudo differential bipolar single-ended ainx+ ainx+ avssx + 0.1v v ref /pga gain 13295-105 figure 87. ? -? adc input signal configur ation, single-ended bipolar v ref /pga gain unipolar single-ended ainx+ ainx+ + 0.1v 13295-106 figure 88. ? -? adc input signal configuration, single-ended unipolar the input signal common mode is not limited, but keep the absolute input signal voltage on any ainx pin between avssx + 100 mv and avdd1x C 100 mv; otherwise, the input signal linearity degrades and, if the signal voltage exceeds the absolute maximum signal rating, damages the device. figure 89 shows the maximum and minimum voltage common- mode range at different pga gains for a maximum differential input voltage. common-mode voltage (v) 1.6500 1.2375 0.8250 0.4125 (avdd1x + avssx)/2 ?0.4125 pga gain 248 1 ?0.8250 ?1.2375 ?1.6500 true differential pseudo differential v ref = 2.5v avdd1x = 1.65v avssx = ?1.65v 13295-107 figure 89. maximum common-mode voltage range for a maximum differential input signal the AD7779 provides a common-mode voltage pin (avdd1x + avssx)/2), vcm, for the single-supply, pseudo differential, or true differential input configurations. transfer function the AD7779 can operate with up to a 3.6 v reference, typical at 2.5 v, and converts the differential voltage between the analog inputs (ainx+ and ainx?) into a digital output. the adc converts the voltage difference between the analog input pins (ainx+ ? ainx?) into a digital code on the output. the 24-bit conversion result is in msb first, twos complement format, as shown in table 15 and figure 90. table 15. output codes and ideal input voltages for pga = 1 condition analog input (ainx+ ? ainx?), v ref = 2.5 v digital output code, twos complement (hex) fs ? 1 lsb +2.499999702 v 0x7fffff midscale + 1 lsb +298 nv 0x000001 midscale 0 v 0x000000 midscale ? 1 lsb ?298 nv 0xffffff ?fs + 1 lsb ?2.499999702 v 0x800001 ?fs ?2.5 v 0x800000 100 ... 000 100 ... 001 100 ... 010 011 ... 101 011 ... 110 011 ... 111 adc code (twos complement) analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb 13295-108 figure 90. transfer function
AD7779 data sheet rev. 0 | page 34 of 97 mclk start - ? modulator signal chain for channel x control block pin control control option pin or spi digital filter sinc3 src gain scaling and offset correction conversion data interface mode0 to mode3 cs sclk sdo sdi sync_out sync_in reset drdy doutx sclk format0 and format1 a inx+ pga gain 1, 2, 4, 8 esd protection ainx? spi control 13295-109 figure 91. top level core signal chain core signal chain each ? - adc channel on the AD7779 has an identical signal path from the analog input pins to the digital output pins. figure 91 shows a top level implementation of this signal chain. prior to each ? - adc, a pga maps sensor outputs into the adc inputs, providing low input current in dc (4 na, input current, and 1.5 na differential input current), an 8 pf input capacitance in ac, and configurable gains of 1, 2, 4, and 8. see the an-1392 for more information. each adc channel has its own ? - modulator, which oversamples the analog input and passes the digital rep- resentation to the digital filter block. the data is filtered, scaled for gain and offset, and is then output on the data interface. to minimize power consumption, the channels can be individually disabled. capacitive pga each ? - adc has a dedicated pga, offering gain ranges of 1, 2, 4, and 8. this pga reduces the need for an external input buffer and allows the user to amplify small sensor signals to use the full dynamic range of the AD7779 . the pga maximize the signal chain dynamic range for small sensor output signals. the AD7779 uses chopping of the pga to minimize offset and offset drift in the input amplifier, reducing the 1/f noise as well. for the AD7779 , the chopping frequency is set to 64 khz for high resolution mode, and 16 khz for low power mode (see the an- 1131 for more information). the chopping tone is rejected by the sinc filter. to minimize intermodulation effects that may cause image in the band of interest, it is recommended to limit the input signal bandwidth to 2/3 of the chop frequency. the capacitive pga common-mode voltage does not depend on the gain, and can be any value as long as the input signal voltage is within avssx + 100 mv to avdd1x C 100 mv. see figure 89 for the maximum common-mode voltage at maximum differential input signals. internal reference and reference buffers the AD7779 integrates a 2.5 v, 10 ppm/c typical, voltage reference that is disabled at power-up. the buffered reference is available at pin 49 and offers up to 10 ma of continuous current. a 100 nf capacitor is required if the reference is enabled. in applications where a low noise reference is required, it is recommended to add a low-pass filter (lpf) with a cutoff frequency (f cutoff ) below 10 hz to the ref_out pin. connect the output of this filter to refx+, and connect avssx to refx?. in this scenario, config-ure the ? - reference as external. an example of performance with and without the output filter is shown in figure 92. 115 105 95 85 75 snr (db) 0.05 0.50 1.00 2.00 2.50 differential input voltage (v) v ref = internal reference f cutoff = 10hz 13295-110 figure 92. snr adding external lpf with v ref = internal reference and f cutoff = 10 hz the AD7779 can be used with an external reference connected between the refx+ and refx? pins. recommended reference voltage sources for the AD7779 include the adr441 and adr4525 family of low noise, high accuracy voltage references.
data sheet AD7779 rev. 0 | page 35 of 97 adc modulator sinc filter data interface control mclk divider high resolution mode: mclk/4 low power mode: mclk/8 dclk divider 1, 2, 4, 8, 16, 32, 64, 128 dec rates = 128, 256, 512, 1024, 2048, 4095.99 mod_mclk dclkx drdy dout3 to dout0 pga ainx+ mclk ainx? 13295-111 figure 93. clock generation on the AD7779 the reference buffers can be operated in three different modes: buffer enabled mode, buffer bypassed mode, and buffer precharged mode. in buffer enabled mode, the buffer is fully enabled, minimizing the current requirements from the external references. note that the buffer output voltage headroom is 100 mv from the rails. in buffer bypassed mode, the external reference is directly connected to the adc reference capacitors; the reference must provide enough current to correctly charge the internal adc reference capacitors. in this mode of operation, a degradation in crosstalk is expected because the adc channels are not isolated from each other. buffer precharged (pre-q) mode is the default operation mode. it is a hybrid mode where the internal reference buffers are connected during the initial acquisition time to precharge the internal adc reference capacitors. during the final phase of the acquisition, the reference is connected directly to the adc capacitors. this mode has some benefits compared to the buffer enabled and buffer bypassed modes. in buffer precharged mode, ? the reference current requirements are minimized compared to buffer bypassed mode ? the noise contribution from the internal reference buffers is removed (compared to buffer enabled mode) in buffer precharged mode, the headroom/footroom of the buffer reference is not applicable because the reference sets the final voltage in the adc reference capacitors. integrated ldos the AD7779 has three internal ldos to regulate the internal supplies: two ldos for the analog block and one ldo for the digital core. the internal ldos requires an external 1 f decoupling capacitor on the dregcap, areg1cap, and the areg2cap pins. the ldo slew rate may be low because it depends on the main supply slew rate; therefore, a hardware reset generated by pulsing the reset pin at power-up is required to guarantee that the digital block initializes correctly. clocking and sampling the AD7779 includes eight ? - adc cores. each adc receives the same master clock signal. the AD7779 requires a maximum external mclk frequency of 8192 khz for high resolution mode and 4096 khz for low power mode. the mclk is internally divided by 4 in high performance mode and by 8 in low power mode to produce the modulator mclk (mod_mclk) signal used as the modulator sampling clock for the adcs. the mclk can be decreased to accommodate lower odrs if the minimum odr selected by the sinc filter is not low enough. if the external clock is lower than 250 khz, set the clk_qual_dis bit (in spi control mode only). the AD7779 integrates an internal oscillator clock that initializes the internal registers at power-up. the clk_sel pin defines the external clock used after initialization (see table 16). table 16. clock sources clk_sel state clock source connection 0 cmos input to xtal2/mclk, iovdd logic level. xtal1 must be tied to dgnd. 1 crystal connected between xtal1 and xtal2/mclk. the mclk signal generates the dclk output signal, which in turn clocks the ? - conversion data from the AD7779, as shown in figure 93. digital reset and synchronization pins an external pulse in the sync_in pin generates the internal reset of the digital block; this pulse does not affect the data programmed in the internal registers. a pulse in this pin is required in two cases as follows: ? after updating one or more registers directly related to the sinc3 filter. these are power mode, offset, gain, and phase compensation. ? to synchronize multiple devices.
AD7779 data sheet rev. 0 | page 36 of 97 the pulse in the sync_in pin must be synchronous with mclk. there are two different ways to achieve a synchronous pulse if the controller/processor cannot generate it as follows: ? applying an asynchronous pulse on the start pin, which is then internally synchronized with the external mclk clock, and the resulting synchronous signal is output on the sync_out pin. ? triggering the sync_out internally. when the AD7779 is configured in spi control mode, toggling bit 0 in the gen_user_config_2 register generates a synchronous pulse that is output on the sync_out pin. the sync_in and sync_out pins must be externally connected if internal synchronization is used. if multiple AD7779 devices must be synchronized, the sync_out pin of one device can be connected to multiple devices. this synchronization method requires the use of a common mclk signal for all the AD7779 devices connected, as shown in figure 94. if the start pin is not used, tie it to dgnd. start sync_in mclk sync_out start sync_in mclk sync_out nc start sync_in mclk sync_out nc AD7779 AD7779 AD7779 synchronization logic asynchronous pulse digital filter synchronization logic digital filter synchronization logic digital filter mclk 13295-112 figure 94. multiple AD7779 synchronization digital filtering the AD7779 offers a low latency sinc3 filter. most precision ? - adcs use sinc3 filters because the sinc3 filter offers a low latency path for applications requiring low bandwidth signals, for example, in control loops or where application specific postprocessing is required. the digital filter adds notches at multiples of the sampling frequency. the digital filter implements three main notches, one at the maximum odr (16 khz or 8 khz, depending on the power mode) and another two at the odr frequency selected to stop noise aliasing into the pass band. figure 95 shows the typical filter transfer function for the high resolution and low power modes using a decimation rate of 256 samples. frequency (khz) gain (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 8 16 24 32 low power mode decimation = 256 high resolution mode decimation = 256 13295-113 figure 95. sinc3 frequency response the sample rate converter featured allows fine tuning of the decimation rate, even for noninteger multiples of the decimation rate. see the sample rate converter (src) section for more information on filter profiles for noninteger decimation rates. shutdown mode the AD7779 can be placed in shutdown mode by pulling avdd2 to ground and connecting 1 m resistance, pulled low, to xtal2. in this mode, the average current consumption is reduced to 1 ma, as shown in figure 96. ?40 ?0.5 0 0.5 1.0 10 temperature (c) 60 125 i avdd1x i avdd2x i avdd4x i iovdd avddx = 3.3v iovdd = 3.3v supply current (ma) 13295-114 figure 96. shutdown current
data sheet AD7779 rev. 0 | page 37 of 97 controlling the AD7779 the AD7779 can be controlled using either pin control mode or spi control mode. pin control mode allows the AD7779 to be hardwired to predefined settings that offer a subset of the overall functionality of the AD7779 . in this mode, the src and diagnostic features or extended errors source are not available. controlling the AD7779 over the spi interface allows the user access to the full monitoring, diagnostic, and ? - control functionality. spi control offers additional functionality such as offset, gain, and phase correction per channel, in addition to access to the flexible src to achieve a coherent sampling. see table 17 for more details about these different configurations. pin control mode in pin control mode, the AD7779 is configured at power-up based on the level of the mode pins, mode 0, mode1, mode2, and mode3. these four pins set the following functions on the AD7779 : the mode of operation, the decimation rate/odr, the pga gain, and the reference source, as shown in table 18. due to the limited number of mode pins and the number of options available, the pga gain control is grouped into blocks of 4, and the odr is selected for the maximum value defined by the decimation rate; odr (khz ) = 2048/decimation for high resolution mode, and odr (khz) = 512/decimation for low power mode. depending on the mode selected, the device is configured to use an external or an internal reference. the conversion data can be read back using the spi interface or the data output interface, as shown in table 17. if the data output interface is used to read back the data from the conversions, the number of doutx lines enabled and the number of clocks required for the ? - data transfer are determined by the logic level of the conv_sar, format0, and format1 pins. in this case, the dclk2, dclk1, and dclk0 pins select the ? - output interface and control the dclkx divide function, which is a submultiple of mclk, as shown in table 19. the dclkx divide function sets the frequency of the data output interface dclkx signal. the dclk minimum frequency depends on the decim- ation rate and operation mode. see the data output interface section for more details about the minimum dclkx frequency. all the pins that define the AD7779 configuration mode are reevaluated each time the sync_in pin is pulsed. the typical connection diagram for pin control mode is shown in figure 97. table 17. format of the data interface conv_sar state format1 format0 control mode data output mode 1 0 0 pin spi output 0 1 pin spi output 1 1 pin spi output 1 1 spi defined in register 0x014 0 0 0 pin dout0, channel 0 to channel 1 dout1, channel 2 to channel 3 dout2, channel 4 to channel 5 dout3, channel 5 to channel 7 0 1 pin dout0, channel 0 to channel 3 dout1, channel 4 to channel 7 1 0 pin dout0, channel 0 to channel 7 1 1 spi defined in register 0x014 table 18. pin mode options pin state decimation rate power mode pga gain channel reference type mode3 mode2 mode1 mode0 channel 0 to channel 3 channel 4 to channel 7 0 0 0 0 1024 high resolution 1 1 external 0 0 0 1 512 high resolution 1 1 external 0 0 1 0 256 high resolution 1 1 external 0 0 1 1 128 high resolution 1 1 external 0 1 0 0 256 high resolution 1 2 external 0 1 0 1 512 high resolution 1 4 external 0 1 1 0 256 high resolution 1 4 external
AD7779 data sheet rev. 0 | page 38 of 97 pin state decimation rate power mode pga gain channel reference type mode3 mode2 mode1 mode0 channel 0 to channel 3 channel 4 to channel 7 0 1 1 1 128 high resolution 1 4 external 1 0 0 0 512 high resolution 1 1 internal 1 0 0 1 256 high resolution 1 1 internal 1 0 1 0 128 high resolution 1 1 internal 1 0 1 1 512 low power 1 1 external 1 1 0 0 256 low power 1 1 external 1 1 0 1 128 low power 1 1 external 1 1 1 0 128 low power 1 1 internal 1 1 1 1 256 low power 1 1 internal table 19. dclkx selection for pin control mode state dclk2/sclk dclk1/sdi dclk0/sdo mclk divider 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 adc data serial interface spi control interface fpga or dsp avdd 3.3v extern a l reference avssx avssx ain7+ ain7? ain0+ ain0? pga vcm avdd1x buffer buffer AD7779 dregcap convst_sar mode3 to mode0 refx+ refx? ref_out avdd4 avssx avssx avdd2x avdd3.3v avdd3.3v iovdd 2v to 3.6v avssx aregxcap avssx avssx iovdd 24-bit - ? adc sinc3/src sync_in drdy sync_out start reset dclk cs sclk sdo clk_sel xtal2 dclk2 to dclk0 xtal1 dout0 dout1 spi/sport slave interface dout2 dout3 spi master interface pga 13295-115 vcm sdi format1 and format0 clock source figure 97. pin mode connection diagram with external reference
data sheet AD7779 rev. 0 | page 39 of 97 adc data serial interface spi control interface fpga or dsp a v dd 3.3v avssx avssx ain7+ ain7? ain0+ ain0? pga vcm avdd1x buffer full buffer buffer AD7779 dregcap convst_sar gpio2 to gpio0 refx+ refx? ref_out avdd4 avssx avdd2x a v dd3.3v iovdd 2v to 3.6v avssx aregxcap avssx avssx iovdd auxain+ auxain? 24-bit - ? adc 12-bit sar adc mux diagnostic inputs sinc3/src sync_in drdy sync_out start reset dclk cs sclk sdo sdi clk_sel format0 xtal2 format1 iovdd iovdd xtal1 dout0 dout1 spi/sport slave interface dout2 dout3 spi master interface pga 13295-116 vcm clock source figure 98. spi control mode connection diagram with internal reference spi control the second option for control and monitoring the AD7779 is via the spi interface. this option allows access to the full functionality on the AD7779 , including access to the sar converter, phase synchronization, offset and gain adjustment, diagnostics and the src. to use the spi control, set the format0 and format1 pins to logic high. in this mode, the spi interface can also be used to read the ? - conversation data by setting the spi_slavemode_en bit. the typical connection diagram for spi control mode is shown in figure 98. functionality available in spi mode spi control of the AD7779 offers the super set of the functions and diagnostics. the spi control functionality section describes the functionality and diagnostics offered when in spi control mode. offset and gain correction offset and gain registers are available for system calibration. the gain register is preprogrammed during final production for a pga gain of 1, but can be overwritten with a new value if required. the gain register is 24 bits long and is split across three registers, chx_gain_upper_byte, chx_gain_mid_byte, and chx_gain_lower_byte, which set the gain on a per channel basis. the gain value is relative to 0x555555, which represents a gain of 1. the offset register is 24 bits long and is spread across three byte registers, chx_offset_upper_byte, chx_offset_mid_ byte, and chx_offset_lower_byte. the default value is 0x000000 at power-up. program the offset as a twos complement, signed 24-bit number. if the channel gain is set to its nominal value of 0x555555, an lsb of offset register adjustment changes the digital output by ?4/3 lsbs. as an example of calibration, the offset measured is ?200 lsb (with both ainx pins connected to the same potential). an offset adjustment of ?150 changes the digital output by ?150 (?4/3) = 200 lsbs (gain value = 0x555555), representing this number as two complement, 0xffffff C 0x96 + 1 = 0xffff70. ? chx_offset_upper_byte = 0xff ? chx_offset_mid_byte = 0xff ? chx_offset_lower_byte = 0x70 note that the offset compensation is performed before the gain compensation. the gain is programmed during final testing for pga gain = 1. the gain register values can be overwritten; however, after a reset or power cycle, the gain register values revert to the hard coded programmed factory setting. if the gain required is 0.75 of the nominal value (0x555555), the value that must be programmed is 0x555555 0.75 = 0x400000 then, an lsb of the offset register adjustment changes the digital output by ?4/3 0.75 = 1 lsb. ? chx_gain_upper_byte = 0x40 ? chx_gain_mid_byte = 0x00 ? chx_gain_lower_byte = 0x00
AD7779 data sheet rev. 0 | page 40 of 97 spi control functionality global control functions the following list details the global control functions of the AD7779: ? high resolution and low power modes of operation ? output data rate: sample rate converter (src) ? vcm buffer power-down ? internal/external reference selection ? enable, precharged, or bypassed reference buffer modes ? internal reference power-down ? sar diagnostic mux ? sar power-down ? gpio write/read ? spi sar conversion readback ? spi slave moderead ? - results ? sdo and dout drive strength ? dout mode ? dclk division ? internal ldo bypassed ? crc protection: enabled or disabled per channel functions the following list details the per channel functions of the AD7779: ? pga gain. ? ? - channel power-down. ? phase delay: synchronization phase offset per channel. ? calibration of offset. ? calibration of gain. ? ? - input signal mux. ? channel error register. ? pga gain. phase adjustment the AD7779 phase delay can be adjusted to compensate for phase mismatches between channels due to sensors or signal channel phase errors connected to the AD7779 . achieve phase adjustment by programming the chx_sync_offset register. this programming delays the synchronization signal by a certain number of modulator clocks, mod_clks, to individually initiate the digital filter for each ? - adc. the phase adjustment register is read during the pulse; conse- quently, any further changes on the register have no effect unless a pulse is generated (see the digital reset and synchronization pins section for more information on how to generate a pulse in the pin). the phase offset register is multiplied internally by a factor that depends on the decimation rate, as shown in table 20. table 20. phase adjustment vs. decimation rate phase adjustment compensation decimation rate 1 255 2 511 4 1023 8 2047 16 4095 the maximum phase delay cannot be equal to or greater than the decimation rate. if this is the case, the value changes internally to the decimation rate value minus 1. as an example, the phase mismatch between channel 0 and channel 1 is 5, and the odr is 5 ksps in high resolution mode. in this case, the decimation ration is 2048 khz/5 khz = 409.6, which means that the offset register value is multiplied internally by 2. assuming an input signal of 50 hz, the number of mod_ mclk pulses required to sample a full period is 2048 khz/ 50 hz = 40960 > 360/40960 = 8.78 10 3 . if a 5 delay is required, the number of mod_mclk delays must be 569 (5/0.00878) because the offset register is multiplied by 2; the final offset register value is 409.6/2 ? 569/2, which gives a negative value. in this case, if the offset value programmed to the register is higher than 204 (for example, 210 2 = 420), the value is internally changed to 408, resulting in a phase compensation of 408 0.00878 = 3.58. pga gain the pga gain can be selected individually by appropriately selecting bits[7:6] in the chx_config register, as shown in table 21. table 21. pga gain settings via chx_config chx_config, bits[7:6] setting pga gain setting 00 1 01 2 10 4 11 8 if the ? - reference is updated, it is recommended to apply a pulse on the sync_in pin to remove invalid samples during the transition of the reference decimation the decimation defines the sampling frequency as follows: ? in high resolution mode, the sampling frequency = mclk/ (4 decimation) ? in low power mode, the sampling frequency = mclk/ (8 decimation) refer to the sample rate converter (src) section for more information.
data sheet AD7779 rev. 0 | page 41 of 97 gpio pins if the AD7779 operates in spi control mode, the mode pins operate as gpio pins, as shown in figure 99. the gpio pins can be configured as inputs or outputs in any order. register map gpio0 gpio1 gpio2 13295-117 figure 99. gpio pin functionality configuration control and readback of the gpio pins are dealt with by bits[2:0] in the gpio_config register (0 = input, 1 = output) and the gpio_data register. among other uses, the gpios can control an external mux connected to the auxiliary inputs of the sar adc. use this mux to verify the results on the ? - adcs. in addition, the gpio pins can be used to externally trigger a new decimation rate. refer to the sample rate converter (src) section for more information about this functionality. ? -? reference configuration the AD7779 can operate with internal or external references. in addition, for diagnostic purposes, the analog supply can be used as a reference, as shown in table 22. table 22. ? - references setting for adc_mux_config, bits7:6 channel 0 to channel 3 channel 4 to channel 7 00 ref1+/ref1? ref2+/ref2? 01 internal reference internal reference 10 avdd1a/avss1a avdd1b/avss1b 11 ref1?/ref1+ ref2?/ref2+ reference buffer operation is described in table 23. the selected reference and buffer operation mode affect all channels. if the ? - reference is updated, it is recommended to apply a pulse on the sync_in pin to remove invalid samples during the transition of the reference. table 23. reference buffer operation modes reference buffer operation mode refx+ refx enabled buffer_config_1, bit 4 = 1; buffer_config_2, bit 7 = 0 buffer_config_1, bit 3 = 1; buffer_config_2, bit 6 = 0 precharged buffer_config_1, bit 4 = 1; buffer_config_2, bit 7 = 1 buffer_config_1, bit 3 = 1; b uffer_config_2, bit 6 = 1 disabled buffer_config_1, bit 4 = 0 buffer_config_1, bit 3 = 0
AD7779 data sheet rev. 0 | page 42 of 97 table 24. additional disable power-down blocks block register notes vcm general_user_config_1, bit 5 enable by default reference buffer buffer_config_1, bits[4:3] precharge mode by default internal reference buffer general_user _config_1, bit 4 disable by default ? -? channel ch_disable, bits[7:0] all channels enable sar general_user_config_1, bit 3 disable by default internal oscillator general_user_c onfig_1, bit 2 enable by default power modes the AD7779 offers different power modes to improve the power efficiency, high resolution and low power mode, which can be controlled via general_user_config_1, bit 6. to further reduce the power, additional blocks can be disabled independently, as described in table 24. if the power mode changes, a pulse on the sync_in pin is required. ldo bypassing the internal ldos can be individually bypassed and an external supply can be applied directly to areg1cap, areg2cap, or dregcap pins. table 25 shows the absolute minimum and maximum supplies for these pins, as well as the associated register used to bypass the regulator. table 25. ldo bypassing ldo buffer_config_2, bits[2:0] 1 supply max (v) min (v) areg1cap 1xx 1.9 1.85 areg2cap x1x 1.9 1.85 dregcap xx1 1.98 1.65 x means dont care. digital spi interface the spi serial interface on the AD7779 consists of four signals: cs , sdi, sclk and sdo. a typical connection diagram of the spi interface is shown in figure 100. dsp/fpga AD7779 cs sclk sdi sdo 13295-118 figure 100. spi control interface? AD7779 is the spi slave, digital signal processor (dsp)/field programmable gate array (fpga) is the master the spi interfaces operates in mode 0 and mode 3, cpol = 0, cpha = 0 (mode 0) or cpol = 1, cpha = 1 (mode 3). in pin control mode, the sdi can be used to read back the ? - results, depending on the level of the conv_sar pin, as described in table 17. in spi control mode, the spi interface transfers data into the on- chip registers while the sdo pin reads back data from the on-chip registers or reads the sar or the ? - conversions results, depending on the selected operation mode. the sdo data source in spi control mode is defined by the general_user_config_2 and general_user_ config_3 registers, as described in table 26. table 26. spi operation mode in spi control mode general_user_ config _ 2, bit 5 setting general_user_ config _ 3, bit 4 setting mode 0 0 internal register 0 1 ? -? data conversion 1 x sar conversion in spi control mode, there are four different levels of i/o strength on the sdo pin, which can be selected in general_user_ config_2, bits[4:3], as described in table 27. table 27. sdo strength general_user_config_2, bits[4:3] setting mode 0 0 nominal 0 1 strong 1 0 weak 1 1 extra strong sclk is the serial clock input for the device. all data transfers (on either sdo or sdi) occur with respect to this sclk signal.
data sheet AD7779 rev. 0 | page 43 of 97 the spi interface can operate in multiples of eight bits. for example, in spi control mode, if the sdo pin is used to read back the data from the internal register or the sar adc, the data frame is 16 bits wide (crc disabled), as shown in figure 101, or 24 bits wide (crc enabled), as shown in figure 102. in this case, the controller can generate one frame of 16 bits/24 bits (with and without the crc enabled), or 2/3 frames of 8 bits (with and without the crc enabled). when the sdo pin is used to read back the data from the ? - channels, 64 bits must be read back from the controller (in this case, the controller can generate a frame of 64 bitseither 2 32 bits, 4 16 bits, or 8 8 bits). spi crcchecksum protection (spi control mode) the AD7779 has a checksum mode that improves spi interface robustness in spi control mode. using the checksum ensures that only valid data is written to a register and allows data read from the device to be validated. the spi crc can be enabled by setting the spi_crc_test_en bit. if an error occurs during a register write, the spi_crc_err is set in the error register. enabling the spi_crc_test_en bit results in a crc checksum being performed on all the r/ w operations. when spi_ crc_test_en is enabled, an 8-bit crc word is appended to every spi transaction for sar and register map operations. for more information on ? - readback operations, see the crc header section. to ensure that the register write is successful, it is recommended to read back the register and verify the checksum. for crc checksum calculations, the following polynomial is always used: x 8 + x 2 + x + 1. see the spi control mode checksum section for more information. spi read/write register mode (spi control mode) the AD7779 has on-board registers to configure and control the device. the registers have 7-bit addressesthe 7-bit register address on the sdi line selects the register for the read/write function. the 7-bit register address follows the r/ w bit in the sdi data. the 8 bits on the sdi line following the 7-bit register address are the data to be written to the selected register if the spi is a write transfer. data on the sdi line is clocked into the AD7779 on the rising edge of sclk, as shown in figure 3. the data on the sdo line during the spi transfer contains the 8-bit 0010 0000 header: 8 bits of register data in the case of a read (r) operation, or 8 zeros in the case of a write ( w ) operation. with the crc disabled, the basic data frame on the sdi line during the transfer is 16 bits long, as shown in figure 101. when the crc is enabled, a minimum frame length of 24 sclks is required on spi transfers. the 24 bits of data on the sdo line consist of an 8-bit header (0010 0000), 8 bits of data, and an 8-bit crc (see figure 102). r/wa6a5a4a3a2a1a0 d6 d7 d5 d4 d3 d2 d1 d0 0 sdo cs sclk sdi 0 1 0 0 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 13295-119 figure 101. 16-bit spi transfercrc disabled r/wa6a5a4a3a2a1a0 d6 d7 d5 d4 d3 d2 d1 d0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 0 sdo cs sclk sdi 0100000r7r6r5r4r3r2r1r0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 13295-120 figure 102. 24-bit spi transfercrc enabled
AD7779 data sheet rev. 0 | page 44 of 97 spi sar diagnostic mode (spi control mode) setting bit 5 in the general_user_config_2 register configures the sdo line to shift out data from the sar adc conversions, as described in table 26. in sar mode, the AD7779 internal registers can be written to, but any readback command is ignored because the sdo data frame is dedicated to shift out the conversion results from the sar adc. to exit this mode of operation, reset bit 5 in the general_ user_config_2 register. the data on the sdo line during the spi transfer contains a 4-bit 0010 header and 12 bits of the sar conversion result if the crc is disabled. when the crc is enabled, a minimum frame length of 24 sclks is required on spi transfers. the 24 bits of data on the sdo line consist of a 4-bit header (0010), 12 bits of data, and an 8-bit crc, as shown in figure 103. per the spi read/write register mode (see the spi read/write register mode section), the sdi line contains the r/ w bit, a 7-bit register address, 8 bits of data, and an 8-bit crc (if enabled). to avoid unwanted writes to the internal register while the sar conversions are read back through the sdo line, it is recom- mended to send a readback command, for example, 0x8000, to the device, which is ignored because the sdo pin is used to shift out the content of the sar adc. if consecutives conversion are performed in the sar adc, read back the result from the previous conversion before a new conversion is generated. otherwise, the results are corrupted. ? -? data, adc mode in pin control mode, the spi interface can be used to read back the ? - conversions as described in table 17. in spi control mode, the spi interface reads back the ? - conversions by setting general_user_config_3, bit 4, as described in table 26; in this mode, the AD7779 internal register can be written to, but any readback command is ignored because the sdo data frame is dedicated to shifting out the conversion results from the ? - adcs. to avoid unwanted writes to the internal register, it is recommended to send a readback command, for example, 0x8000, to the device, which is ignored because the sdo pin is used to shift out the content of the ? - adc. the sdo pin data can be read back in any multiple of 8 bits, for example, as 64 bits, 2 32 bits, 4 16 bits, or 8 8 bits. spi software reset keeping the sdi pin high during 64 consecutives clocks generates a software reset. r/wa6a5a4a3a2a1a0 d6 d7 d5 d4 d3 d2 d1 d0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 0 sdo cs sclk sdi 010 sar 11 sar 10 sar 9 sar 8 sar 6 sar 7 sar 5 sar 4 sar 3 sar 2 sar 1 sar 0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 13295-121 figure 103. sar adc/diagnostic modecrc enabled
data sheet AD7779 rev. 0 | page 45 of 97 diagnostics and monitoring self diagnostics error the AD7779 includes self diagnostic features to guarantee the correct operation. if an error is detected, the alert pin is pulled high to generate an external interruption to the controller. in addition, the header of the ? - output data contains a bit used to inform the controller of a chip error (see the adc conversion outputheader and data section). both the alert pin and the bit (status header) are automatically cleared if the error is no longer present. the errors related to the spi interface do not recover automatically; read back the appro- priate register to clear the error, resetting both the alert pin and the bit. if an error detector is manually disabled, it does not generate an internal error and, consequently, the register map or the alert pin and bit are not triggered. there are different sources of errors, as described in table 28. in pin control code, it is not possible to check the error source, and some sources of error are not enabled. in spi control mode, check the source of an error by re ading the appropriate register bit. the status_reg_x register bits identify the register that generates an error, as summarized in table 28. table 28. register error source bit name register source err_loc_gen2 gen_err_reg_2 err_loc_gen1 gen_err_reg_1 err_loc_ch7 ch7_err_reg err_loc_ch6 ch6_err_reg err_loc_ch5 ch5_err_reg err_loc_ch4 ch4_err_reg err_loc_ch3 ch3_err_reg err_loc_ch2 ch2_err_reg err_loc_ch1 ch1_err_reg err_loc_ch0 ch0_err_reg err_loc_sat_ch6_7 ch6_7_sat_err err_loc_sat_ch4_5 ch4_5_sat_err err_loc_sat_ch2_3 ch2_3_sat_err err_loc_sat_ch0_1 ch0_1_sat_err in addition, status_reg_x has a bit that indicates if any internal error bit is set. this bit clears if the error is no longer present and the register is read back. the init_complete bit in th e status_reg_3 indicates that the device is initialized correc tly. this bit is not an error but an indicator. general errors mclk switch error (spi control mode) after power-up, the AD7779 initiates a clocking handover sequence to pass clocking control to the external oscillator, or the cmos clock. in spi mode, if an error occurs in the handover, the ext_mclk_switch_err bit is set in the general error register, gen_err_reg_2. if ext_mclk_switch_err is set, this means that the device is operating off the internal oscillator. to use a slow external clock (<265 khz), set the clk_qual_ dis bit. setting this bit also clears the error bit. if the external clock is between 132 khz and 265 khz, depending on the internal synchronization between internal oscillator and external clock, the error may not trigger. however, it is still recommended to set the clk_qual_dis bit. if a slow clock is not in use and the error triggers, a reset is required. reset detection the AD7779 general error register contains a reset_detec- ted bit. this bit is asserted if a reset pulse is applied to the AD7779 and is cleared by reading the general error register. this bit indicates that the power-on reset (por) initialized correctly on the device. in addition, this pin can be used to detect an unexpected device reset or glitch on the reset pin. to reset this error signal in spi control mode, toggle the sync_in pin or read from the general error register, gen_err_reg_2. to reset this error signal in pin control mode, toggle the sync_in pin. internal ldo status the AD7779 has three internal ldos to regulate the internal analog and digital supply rails. the ldos have internal power supply monitors. internal comparators monitor and flag errors with these supplies after they pass a predetermined limit. the aldo1_psm_err, aldo2_psm_err, and dldo_psm_ err bits indicate either an ldo malfunction, or, if the ldos are bypassed, an incorrect external supply. the internal analog and digital voltage monitors can be disabled by appropriately selecting the ldo_psm_test_en bits. use the sar adc to verify the error. additionally, the levels of the internal monitors can be manually triggered to check if the detector works correctly by appropriately setting the bits in the ldo_psm_trip_test_en register. these bits increase the comparator window threshold above the ldo outputs, forcing the comparator to trigger. rom and memmap crc if an error is found at power-up during the rom verification, or if the internal memory map is corrupted, the AD7779 generates an error and sets memmap_crc_err or rom_ crc_err, depending on the source of the error. the checker can be disabled by clearing the memmap_ crc_test_en and rom_crc_test_en bits. the device must be reset if any of these errors trigger.
AD7779 data sheet rev. 0 | page 46 of 97 ? -? adc errors reference detect (spi control mode) in spi control mode, the AD7779 includes on-chip circuitry to detect if there is a valid reference for conversions or calibrations. if the voltage between the selected refx+ and refxC pins goes below 0.7 v, the AD7779 detects that it no longer has a valid reference. chx_err_ref_det can be interrogated to identify the affected channel, which clears the bit register if the error is no longer present. the voltage detector can be disable by clearing the ref_det_test_en bit. use the ? - adc diagnostic or the sar adc to verify the error. overvoltage and undervoltage events the AD7779 includes on-chip overvoltage/undervoltage circuitry on each analog input pin. when the voltage on an analog input pin goes above avdd1x + 0.04 mv, the chx_ err_ainx_ov bit is set. the error disappears if the input voltage falls below avdd1x C 40 mv. if an undervoltage event occurs (avssx C 40 mv), the chx_ err_ainx_uv bit is set. the error disappears if the input voltage increases to avssx + 0.04 v. the chx_err_ainm_uv, chx_err_ainm_ov, chx_err_ ainp_uv, and chx_err_ainp_ov bits can be read back to verify the affected channel input, which clears the bit register if the error is no longer present. the overvoltage and undervoltage detection can be disabled independently by clearing the ainm_ uv_test_en, ainm_ov_test_en, ainp_uv_test_en, or ainp_ov_test_en bits. the input voltage can be checked independently with the sar adc. modulator saturation the AD7779 includes modulator saturation detection on each of the ? - adcs. if 20 consecutive codes for the modulator are either all 1s or 0s, this is flagged as a modulator saturation event. reading the chx_err_mod_sat register clears the bit if the error corrects itself. modulator saturation detection can be disabled by clearing the mod_sat_test_en bit. note that the modulator input voltage is attenuated internally, which means that a modulator output of all 1s or 0s represents a modulator that is out of bounds and that a reset pulse is required. filter saturation the AD7779 includes digital filter saturation detection on each ? - adc channel. this detection indicates that the filter output is out of bounds, which represents an output code approximately 20% higher than positive or negative full scale. reading the chx_err_ filter_sat bit clears the bit if the error corrects itself. the detection can be disabled by clearing filter_sat_test_ en bit. output saturation an output saturation event can occur when gain and offset calibration causes the output from the digital filter to clip at either positive or negative full scale. the output does not wrap. reading the chx_err_output_sat bit clears the bit if the error corrects itself. the detection can be disabled by clearing output_sat_ test_en bit. spi transmission errors (spi control mode) all spi errors clear after reading gen_err_reg_1, which contains the spi errors. these errors are not recovered auto- matically and, consequently, the alert pin and the alert bit remain set until the error register is read back. crc checksum error if the crc checksum is enabled by setting the spi_crc_ test_en bit, an error bit, spi_crc_err, is raised if the crc message does not match the message computed by the AD7779 internal crc block. if the crc message does not match the internally computed message, the register is not updated. sclk counter if the number of clocks generated by the controller is not a multiple of 8 after cs is pulled high, an error bit, spi_clk_ count_err is raised. the last command multiple of 8 is executed; however, the sclk counter can be disabled by setting the spi_clk_count_test_en bit. invalid read when an invalid register is trying to read back, the spi_invalid_ read_err bit is set. the invalid readback address detection can be disabled by setting the spi_invalid_read_test_en bit. invalid write when an invalid register is trying to write, the spi_invalid_ write_err bit is set. the invalid write address detection can be disabled by setting the spi_invalid_write_test_en bit. monitoring using the AD7779 sar adc (spi control mode) the AD7779 contains an on-chip sar adc for chip diagnostics, system diagnostics, or measurement verification. the sar adc has a 12-bit resolution. the avdd4 and avss4 pins operate in complete independence of the ? - adc supplies and, therefore, can be used for chip diagnostics in systems where functional safety is important. the reference for the sar conversion process is taken from the sar adc supply voltage (avdd4/ avss4) and, therefore, the sar analog input range is from avss4 to avdd4. the sar adc has a maximum throughput rate of 256 ksps. the convst_sar pin initiates a conversion on the sar adc. the maximum allowable frequency of the convst_sar pin is
data sheet AD7779 rev. 0 | page 47 of 97 256 khz. if consecutives conversion are performed in the sar adc, read back the result from the previous conversion before a new conversion is generated. otherwise, the results are corrupted. the sar adc is only available in spi control mode. to read conversion results from the sar adc, set the sar_diag_ mode_en bit. after this bit is set, all data shift out from the sdo pin are from the sar adc register, as shown in figure 104. the convst_sar signal can be internally deglitched to avoid false triggers. table 29. sar synchronization and deglitching convst_ deglitch_dis effect on convst_sar 11 convst_sar goes directly to the sar 10 convst_sar reaches the sar when it is 1.5 mclk cycles wide increase the acquisition time by 1.5/mclk when the deglitch circuitry is enabled. prior to the sar adc, the AD7779 contains an internal multiplexer. this multiplexer can be configured over the spi interface to set the inputs to the sar adc to be either internal circuit nodes in the case of diagnostics or to select the external auxain+ and auxain? pins. along with converting external voltages, the sar adc can be used to monitor the internal nodes on the avdd, iovdd, and dgnd pins, and can monitor the dldo and aldo outputs. some voltages are internally attenuated by 6, and the resulting voltage is applied to the sar adc, as shown in table 30. this is useful because variations in the power supply voltage can be monitored. the input multiplexer of the sar is controlled by the global_ mux_config register, and the different inputs available are described in table 30. the sar adc also contains an adc driver amplifier, as shown in figure 105. this amplifier settles the sar input to 12-bit accuracy within the t 33 time. this driver amplifier helps minimize the kickback from the sar converter to the global diagnostic mux input circuit nodes. use the auxiliary inputs, auxain+ and auxain?, to validate the ? - measurements. while operating in spi control mode, the AD7779 has three available gpio ports controlled via the spi interface. the gpio pins can be used to control an external, dual 8:1 multiplexer, which in turn is used to sample the eight ? - channels. use this diagnostic in applications where functional safety is required. this diagnostic aids in removing the need for a secondary external adc to validate primary measurements on the ? - channels. temperature sensor the internal die temperature can be measured with an error of 2c. dv be is proportional to the temperature measured referred to 25c. temperature (c) = mv2 v6.0 ? table 30. sar mux inputs sar input positive signal negative signal attenuation 6 0 auxain+ auxain? no 1 dv be avssx no 2 ref1+ ref1? no 3 ref2+ ref2? no 4 ref_out avssx no 5 vcm avssx no 6 areg1cap avssx yes 7 areg2cap avssx yes 8 dregcap dgnd yes 9 avdd1a avssx yes 10 avdd1b avssx yes 11 avdd2a avssx yes 12 avdd2b avssx yes 13 iovdd dgnd yes 14 avdd4 avssx no 15 dgnd avssx yes 16 dgnd avssx yes 17 dgnd avssx yes 18 avdd4 avssx yes 19 ref1+ avssx no 20 ref2+ avssx no 21 avssx avdd4 yes cs sdi sdo set bit 5 general_user_config_2 reg write to adc mux register write to adc mux register adc conversion result reg adc conversion result reg 13295-123 figure 104. configuring the AD7779 to operate the spi to read from the sar adc
AD7779 data sheet rev. 0 | page 48 of 97 sar driver control logic fifo on-chip diagnostics spi auxain+ auxain? a v dd4 avss4 convst_sar mux deglitch sar adc ref 13295-122 figure 105. sar adc configuration and control table 31. ? - diagnostic input voltage recommended voltage reference notes/result 0 floating not applic able not applicable 1 floating not applic able not applicable 2 280 mv differential signal internal/external pga gain calibration 3 external reference, positive/negative external positive full scale 4 external reference, negative/pos itive external negative full scale 5 external reference, negative/ negative external zero scale 6 internal reference, positive/negative internal positive full scale 7 internal reference, negative/positive internal negative full scale 8 internal reference, positive/ positive internal zero scale 9 external reference, positive/ positive external zero scale - adc diagnostics (spi control mode) the AD7779 ? - adc diagnostic functions are accessible through the spi interface. the internal mux placed before the pga has different inputs, allowing the user to select a zero-scale, positive full-scale, or negative full-scale input to the ? - adc, which can be converted to verify the correct operation of the ? - adc channel. the diagnostic mux control signals are shared across all the ? - channels. depending on the diagnostic selected, connect the ? - adc reference to a different reference source to guarantee that the conversion is within the measurable range. there are two different ways to enable the diagnostic mux: ? setting the chx_rx bit. this bit enables the input ? - mux. the multiplexer inputs are described in table 31. the reference used during the conversions are controlled by the ref_mux_ctrl bits. ? setting chx_ref_monitor. this bit has the same effect as enabling the chx_rx bit and selects the vdd1x/ avssx supplies as the main reference. if the ainx pin is connected to avssx, the input range is outside range (avssx + 100 mv); therefore, results may differ slightly from the expected value. the inputs can be used alternatively to calibrate gain and offset errors.
data sheet AD7779 rev. 0 | page 49 of 97 ? - output data adc conversion outputheader and data the AD7779 ? - conversion results are output on the dout0 to dout3 pins or over the spi, depending on the selected interface. if the doutx interface is selected, the ad7770 acts as the master in the transmission. if the spi interface is selected, the controller is the master. the drdy signal indicates the end of conversion independently of the interface selected to read back the ? - conversion. when the spi is used to read back the ? - conversion, if a new conversion is completed ( drdy falling edge) before the previous conversion is read back, the results from previous conversion are overwritten and, consequently, the previous conversion data is corrupted. for each channel, the width is 32 bits long: 8 bits for the header and 24 bits for the ? - conversion, as shown in figure 106. adc data n n ? 1 24-bits 8-bits doutx drdy header n 13295-124 figure 106. adc output8-bit header + 24-bit conversion data in pin control mode, the header is fixed to the crc while in spi mode, and can be selected between crc or error headers. crc header the crc header is the header generated in pin control mode or in spi mode if dout_header_format is set. as shown in figure 107, the header consists of a chip error bit, three bits for the adc channel, as shown in table 32, and four bits for the crc. the chip error bit is set high if an error is detected in any channel, as explained in the general errors section. the chip error bit remains 1 until the error disappears. chip error channel number channel number channel number crc crc crc crc 13295-200 figure 107. crc header table 32. channel id channel channel id 2 channel id 1 channel id 0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 the crc generated is eight bits long; the crc 4 msbs are placed on the header for the first channel in the pairing and the 4 lsbs on the header of the second channel in the pairing, as shown in table 33. if a channel is disabled, the 24-bit output data for this channel is 0x000000. table 33. 8-bit crc, header configuration (channel 2) channel 2 header ce 0 1 0 crc7 crc6 crc5 crc4 table 34. 8-bit crc, header configuration (channel 3) channel 3 header ce 0 1 1 crc3 crc2 crc1 crc0 error header (spi control mode) in spi control mode, the default header can be replaced by an error header. if the ? - conversion is read back through the spi interface, disable the crc by clearing the spi_crc_test_en bit. if the doutx interface is used, clear the dout_header_ format bit. the error header provides information of common error sources specific for each channel, as shown in table 35. modulator and filter errors are indicated even if the checker for this error has been specifically disabled, as described in the ? - adc errors section. table 35. status header output bits name description 7 alert this bit is set high if any of the enabled diagnost ic functions have detected an error, including an external clock not detected, a memory map bit flip, or an internal crc error. this bit is not channel specific. the bit clears if the error is no longer present. 6:4 ch_id_[2:0] these bits indicate which adc channel th e following conversion data came from (see table 32). 3 reset_detected this bit indicates if a reset condition occurs. this bit is not channel specific. 2 modulator_saturate this bit indicates that the modulator output 20 consec utive 0s or 1s. the bit resets automatically after the error is no longer present. 1 filter_saturate this bit indicates that the filter output is out of bou nds. the bit resets automatically after the error is no longer present. 0 ain_ov_uverror this bit indicates that there is an ainx overvoltag e/undervoltage condition on the inputs. this bit is set until the appropriate register is read back and the error is no longer present.
AD7779 data sheet rev. 0 | page 50 of 97 sample rate converter (src) (spi control mode) the AD7779 implements a patented featured called the src on each ? - channel, which allows the user to configure the output data rate or sampling frequency to any desired value, including noninteger values. the src achieves fine resolution control over the ? - adc odr, up to 15.2 sps. in applications where the odr must change based on changes in the input signal to maintain sampling coherency, the src provides fine control over the odr. for example, to achieve the highest classification standard, class a, in power quality applications, coherency must be maintained for 0.01 hz changes in the input power line. the src can be used to achieve this sampling frequency accuracy. in the pin control mode, the odr is fixed per the predefined pin control options. consequently, a noninteger number cannot be selected, as shown in table 17. to set the odr, the user must program up to four registers, depending on the decimation value: two registers to program the integer value, n (the effective decimation rate), and two registers to program the decimal value, if (the inter-polation factor). the integer value registers are src_n_msb, bits[3:0] and src_n_lsb, bits[7:0]. the decimal part value registers are src_if_msb, bits[7:0] and src_if_lsb, bits[7:0]. as an example, if an output data rate of 2.8 khz is required, which equates to ? hp mode = 2048/2.8 = 731.428 ? low power mode = 512/2.8 = 182.857 the register values for hp mode are as follows: ? 731d = 0x2db ? src_n_msb[3:0] = 0x02 ? src_n_lsb[7:0] = 0xdb ? 0.428d = 0.428 2 16 = 28049d = 0x6d91 ? src_if_msb[7:0] = 0x6d ? src_if_lsb[7:0] = 0x91 the odr can be updated on the fly, but a new odr is effective in three conversion cycles of the ? - adcs. this guarantees a smooth transition with no conversion results out of range. there are two different ways to change the odr after a new value is written in the src registers: via software or via hardware, depending on src_update, bit 7. if the src_load_source bit is clear, the new odr value is updated by setting the src_load_update bit to 1. this bit must be held high for at least two mlck periods; return the bit to 0 before attempting another update. if src_load_source is set, the odr update is controlled externally by the gpio0 pin. apply a pulse in the gpio2 pin, which is then internally synchronized with the external mclk clock, and the resultant synchronous signal is output on the gpio1 pin. the gpio1 and gpio0 pins must be externally connected. if multiple AD7779 must be synchronized, the gpio1 pin of one device can be connected to multiple devices. this synch- ronization method requires the use of a common mclk signal for all the AD7779 devices connected, as shown in figure 108. gpio2 gpio0 gpio0 gpio0 mclk gpio1 gpio2 mclk gpio1 nc gpio2 mclk gpio1 nc AD7779 AD7779 AD7779 synchronization logic pulse digital filter synchronization logic digital filter synchronization logic digital filter mclk 13295-125 figure 108. hardware odr update src bandwidth the sinc filter architecture allows the user to select a noninteger value as the decimation range this versatility means that the filter notches must be adjusted dynamically: two notches at the variable frequency, and one fixed notch to remove the pga chopping tone. consequently, the traditional formula for the ?0.1 db and ?3 db bandwidth must be adjusted depending on the selected decimation rate. the bandwidth transfer function is not linear but can be approximated by using a linear function.
data sheet AD7779 rev. 0 | page 51 of 97 figure 109 and figure 110 show the correction factor for the ?0.1 db and ?3 db bandwidth, respectively. in low power mode, the offset must be divided by 4. for example, when the odr = 1000, the ?0.1 db point is bw = 0.0581 1000 + 4 9271.2 = 59 hz 13295-126 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 10 12 14 16 18 ?0.1db frequen c y (hz) odr (khz) y = 0.0581x + 2.9271 figure 109. ?0.1 db correction factor 6 5 4 3 ?3db frequency (khz) 2 1 odr (khz) 0 13295-127 1357911131517 y = 0.3135x + 13.99 figure 110. ?3 db correction factor src group delay the src group delay depends on the selected odr and the power mode, and is defined by the following equation: group delay = odrnsrc nsrcpm ? ? _ _ where: pm is a value that depends on the power mode, either 64 for high resolution mode or 32 for low power mode. src_n is the integer value of the programmed odr. odr is the programmed output data rate. settling time the settling time is defined by the contribution of all the internal stages, the filter delay, and the block calibration. the filter delay is defined as 3/odr. in some extreme cases, as when an external pulse is applied, this value may increase to 4/odr. in high resolution mode, the calibration delay is defined as 62 t mclk , with a maximum error of 2 t mclk . in low power mode, the calibration delay is defined as 121 t mclk , with a maximum error of 4 t mclk . t mclk is the modulator period and is 488 ns in high resolution mode and 1.9 s in low power mode. data output interface the ? - output data interface is defined by theconv_sar, format0, and format1 pins in pin control mode at power-up. the formatx pins cannot be changed dynamically. table 18 shows the available options for pin control mode. if the device is configured in spi control mode, the spi_slave_mode_ en bit enables the spi interface to transmit the ? - adc conversion results, as shown in table 26. dout3 to dout0 data interface standalone mode in standalone mode, the AD7779 interface acts as a master. there are three different dout configurations, configurable through the formatx pins in pin control mode, as shown in figure 111 through figure 113, or via the dout_format bits, bits[7:6], in spi control mode, as described in table 36. figure 114, figure 115, and figure 116 show the expected data outputs for different doutx output modes.
AD7779 data sheet rev. 0 | page 52 of 97 table 36. doutx channels dout_format bits/ formatx pins number of doutx lines enabled associated channels 00 4 dout0channel 0 and channel 1 dout1channel 2 and channel 3 dout2channel 4 and channel 5 dout3channel 6 and channel 7 01 2 dout0channel 0, channel 1, channel 2, and channel 3 dout1channel 4, channel 5, channel 6, and channel 7 10 1 dout0channel 0, channel 1, channel 2, channel 3, channel 4, channel 5, channel 6, and channel 7 dout0 dout1 dout2 dout3 dclk drdy format1 daisy-chaining is not possible in this format format0 AD7779 ch 0 ch 1 ch 0 ch 1 ch 0 ch 1 ch 0 ch 1 13295-128 dgnd dout0: ch 0, ch 1 dout1: ch 2, ch 3 dout2: ch 4, ch 5 dout3: ch 6, ch 7 0 0 00 figure 111. formatx pin configurationforma t0 = 0, format1 = 0 dout0 dout1 dclk drdy format1 iovdd daisy-chaining is possible in this format dgnd format0 ch 0, ch 1, ch 2, ch 3 output on dout0 ch 4, ch 5, ch 6, ch 7 output on dout1 01 1 0 AD7779 ch 4 ch 5 ch 6 ch 7 ch 0 ch 1 ch 2 ch 3 13295-129 figure 112. formatx pin configurationforma t0 = 1, format1 = 0 dout0 dclk drdy format1 iovdd daisy-chaining is possible in this format dgnd format0 ch 0 to ch 7 o utput on dout0 10 0 1 AD7779 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13295-130 figure 113. formatx pin configurationforma t0 = 0, format1 = 1
data sheet AD7779 rev. 0 | page 53 of 97 ch0-s0 ch1-s0 ch2-s0 ch3-s0 ch0-s1 ch1-s1 ch2-s1 ch3-s1 dclk drdy dout0 sample n sample n + 1 dout1 ch4-s0 ch5-s0 ch6-s0 ch7-s0 ch4-s1 ch5-s1 ch6-s1 ch7-s1 dout0 dout1 13295-131 figure 114. format0 = 0, format1 = 0ea ch doutx outputs two adc conversions (s0 means sample 0 and s1 means sample 1) ch0-s0 ch1-s0 ch2-s0 ch3-s0 ch7-s0 ch4-s0 ch5-s0 ch6-s0 ch0-s1 ch1-s1 ch2-s1 ch3-s1 ch7-s1 ch4-s1 ch5-s1 ch6-s1 dclk drdy dout0 sample n sample n + 1 dout1 dout3 dout2 13295-132 figure 115. format0 = 0, format1 = 1channel 0 to channel 3 share dout0, and channel 4 to channel 7 share dout1 (s0 means sampl e 0 and s1 means sample 1) dclk drdy dout0 sample n sample n + 1 sample n + 2 dout3 dout2 dout1 ch0-s0 ch1-s0 ch2-s0 ch...-s0 ch6-s0 ch7-s0 ch0-s1 ch0-s2 ch0-s3 ch1-s1 ch2-s1 ch...-s1 ch6-s1 ch7-s2 ch1-s2 ch2-s2 ch...-s2 ch6-s2 ch7-s2 13295-133 figure 116. format0 = 1, format1 = 0channel 0 to channel 7 output on dout0 only (s0 means sample 0 and s1 means sample 1)
AD7779 data sheet rev. 0 | page 54 of 97 daisy-chain mode daisy-chaining devices allows numerous devices to use the same data interface lines by cascading the outputs of multiple adcs from separate AD7779 devices. in daisy-chain config- uration, only one device has direct connection between the doutx interface and the digital host. for the AD7779 , daisy- chain capability is implemented by cascading dout0 and dout1 through a number of devices, or by just using dout0 (this depends on the selected doutx mode). the ability to daisy chain devices and the limit on the number of devices that can be handled by the chain is dependent on the selected doutx mode and the decimation rate employed. when operating in daisy-chain mode, it is required that all AD7779 devices in the chain are correctly synchronized. see the digital reset and synchronization pins section for more information. this feature is especially useful for reducing the component count and wiring connections in, for example, isolated multiconverter applications or for systems with a limited interfacing capacity. for daisy-chain operation, there are two different configurations possible, as described in table 37. using the doutx = 10 mode dout2 acts as input pins, as shown in figure 117. in this case, the dout0 pin of the AD7779 devices is cascaded to the dout2 pin of the next device in the chain. data readback is analogous to clocking a shift register where data is clocked on the rising edge of dclk. table 37. doutx modes in daisy-chain operation dout_format bits/ formatx pins number of doutx lines enabled associated channels 01 2 dout0channel 0 to channel 3 and dout2 d out1channel 4 to channel 7 and dout3 dout2input channel dout3input channel 10 1 dout0channel 0 to channel 7 and dout2 d out2input channel u2 s0 ch0 to ch7 u2 s0 ch0 to ch7 u1 s0 ch0 to ch7 0 0 u2 s0 ch0 to ch7 u1 s0 ch0 to ch7 0 u2 s1 ch0 to ch7 u2 s1 ch0 to ch7 u1 s1 ch0 to ch7 0 0 u2 s1 ch0 to ch7 u2 s3 ch0 to ch7 0 u2 s0 ch0 to ch7 u2 s0 ch0 to ch7 u1 s1 ch0 to ch7 0 u2 dout0 u1 dout2/din0 u1 dout0 u2 dout2/din0 drdy dclk u2 dout2/din0 dout0 u2 dout2/din0 dout0 13295-134 fi gure 117. daisy-chain connection mode, format0 = 1, format1 = 0 (s0 means sample 0 and s1 means sample 1); when connected in daisy-chain mode, dout2 acts as an input pin, represented by din0
data sheet AD7779 rev. 0 | page 55 of 97 minimum dclkx frequency select the dclkx frequency ratio in such a way that the data is completely shifted out before a new conversion is completed, otherwise the previous conversion is overwritten and the trans- mission becomes corrupt. the minimum dclkx frequency ratio is defined by the decimation rate, the operation mode, and the lines enabled on the dout3 to dout0 data interface as described in the following equations: in standalone mode, high resolution mode ? dclk min_ratio < decimation / (8 channels_per_dout ) low power mode ? dclk min_ratio < decimation / (4 channels_per_dout ) in daisy-chain mode, high resolution mode ? dclk min_ratio < decimation / (8 devices doutx channels ) low power mode ? dclk min_ratio < decimation / (4 devices doutx channels ) as an example, when operating in master interface mode, doutx = 01, the dout0 and dout1 pins shift out four - channels each and, assuming a maximum output rate in high resolution mode, the decimation = 128. dclk min < 128/ (8 4) = 4 if the dclk min_ratio is selected above the necessary minimum, a logic 0 is continuously transmitted until a new sample is available. an example in daisy-chain mode, assuming doutx = 01, and with three devices connected and a decimation rate of 256 in high resolution mode, is as follows: dclk min_ratio < 256/(8 3 4) = 2.66 = 2 the different ratios are summarized in table 38. table 38. available dclk ratios dclk_clk_div (spi control mode), dclkx (pin control mode) dclkx ratio 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 there are maximum achievable odrs and minimum dclkx frequencies required for a given doutx pin configuration, as shown in table 39 and table 40. table 39. maximum odrs and minimum dclkx frequencies in high resolution mode decimation rate odr (ksps) minimum dclkx (khz) 1 doutx 2 doutx 4 doutx 4095 0.500122 128 64 32 2048 1 256 128 64 1024 2 512 256 128 512 4 1024 512 256 256 8 2048 1024 512 128 16 4096 2048 1024 table 40. maximum odrs and minimum dclk frequencies in low power mode decimation rate odr (ksps) minimum dclk (khz) 1 dout 2 dout 4 dout 2048 0.25 64 32 16 1024 0.5 128 64 32 512 1 256 128 64 256 2 512 256 128 128 4 1024 512 256 if the AD7779 operates in spi control mode, it is possible to adjust the doutx strength, which can be selected in the dout_drive_str bits, as described in table 41. table 41. doutx strength general_user_config2, bits[2:1] mode 0 0 nominal 0 1 strong 1 0 weak 1 1 extra strong spi interface the spi interfaces gives the user flexibility to read the conversion from the ? - adc where the processor or microcontroller is the master. when a new conversion is completed, the drdy signal is toggled to indicate that data can be accessed. when drdy toggles, the internal channel counter is reset and the next spi read is from channel 0 again. conversely, after the last channel data is read, all succeding reads before the next drdy signal are from channel 7 (lsb).
AD7779 data sheet rev. 0 | page 56 of 97 ch0_header _+_ch0_8_bits_msb ch0_16_bits_lsb 13295-135 cs sdo figure 118. spi readback , 16 bits per frame cs sdo ch0_header _+_ch0_16_bits_msb ch0_8_bits_lsb_+_ch1_header_+ch1_8_bits_msb 13295-136 figure 119. spi readback , 24 bits per frame the spi operates in multiples of 8 bits per frame; figure 118 shows a readback example in 16 bits per frames, whereas figure 119 shows a readback in 24 bits per frame. note that if the device is configured in spi control mode, the AD7779 generates a software reset if the sdi pin is sampled high for 64 consecutive clocks. to avoid a reset or unwanted register writes, it is recommended to transfer a 0x8000 command, which generates a readback command that is ignored by the device, as explained in the spi software reset section. calculating the crc checksum the AD7779 implements two different crc checksum generators, one for the ? - results and another for the spi control mode. the AD7779 uses a crc polynomial to calculate the crc checksum value. the 8-bit crc polynomial used is x 8 + x 2 + x + 1. the polynomial is aligned so that its msb is adjacent to the leftmost logic 1 of the data. an xor (exclusive or) function is applied to the data to produce a new, shorter number. the poly- nomial is again aligned so that its msb is adjacent to the leftmost logic 1 of the new result, and the procedure is repeated. this process is repeated until the original data is reduced to a value less than the polynomial. this is the 8-bit checksum. as an example of crc calculation for 12-bit data is shown in table 42. table 42. example crc calculation for 12-bit data 1 data 0 1 1 0 0 1 0 0 1 1 1 0 polynomial 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 0 0 0 0 0 1 1 crc 0 1 0 1 1 1 1 0 1 this table represents the division of the data; blank cells are for formatting purposes. ? -? crc checksum the crc message is calculated internally by the AD7779 on adc pairs. the crc is calculated using the adc output data from two adcs and bits[7:4] from the header. therefore, 56 bits are used to calculate the 8-bit crc. this crc is split between the two channel headers. the crc data covers channel pairings as follows: channel 0 and channe l 1, channel 2 and channel 3, channel 4 and channel 5, channel 6 and channel 7. to generate the checksum, the data is left shifted by eight bits to create a number ending in eight logic 1s. the crc is calculated from 56 bits across two consecutive/ channel pairings (channel 0 and channel 1, channel 2 and channel 3, channel 4 and channel 5, channel 6 and channel 7). the 56 bits consist of the chip error, the 3 bits for the first adc pairing channel, and the 24 bits of data of each pairing channel. for example, for the second channel pairing, channel 2 and channel 3, 56 bits = chip error + 3 adc channel bits (010) + 24 data bits (channel 2) + chip error + 3 adc channel bits (011) + 24 data bits (channel 3) spi control mode checksum the crc message is calculated internally by the AD7779. the data transferred to the AD7779 uses the r/w bit, a 7-bit address, and 8 bits of data for the crc calculation. the crc calculated and appended to the data that it is shifted out uses a 0010 0000 header and 8 bits of data for the register readback, as well as the 0010 header and 12 bits of sar conversion data for the sar readback transfers.
data sheet AD7779 rev. 0 | page 57 of 97 register summary table 43. AD7779 register summary reg. name bits bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x000 ch0_config [7:0] ch0_gain ch0_ref_ monitor ch0_rx reserved 0x00 /w r 0x001 ch1_config [7:0] ch1_gain ch1_ref_ monitor ch1_rx reserved 0x00 r/w 0x002 ch2_config [7:0] ch2_gain ch2_ref_ monitor ch2_rx reserved 0x00 r/w 0x003 ch3_config [7:0] ch3_gain ch3_ref_ monitor ch3_rx reserved 0x00 r/w 0x004 ch4_config [7:0] ch4_gain ch4_ref_ monitor ch4_rx reserved 0x00 r/w 0x005 ch5_config [7:0] ch5_gain ch5_ref_ monitor ch5_rx reserved 0x00 r/w 0x006 ch6_config [7:0] ch6_gain ch6_ref_ monitor ch6_rx reserved 0x00 r/w 0x007 ch7_config [7:0] ch7_gain ch7_ref_ monitor ch7_rx reserved 0x00 r/w 0x008 ch_disable [7:0] ch7_ disable ch6_ disable ch5_disable ch4_ disable ch3_ disable ch2_ disable ch1_ disable ch0_ disable 0x00 r/w 0x009 ch0_sync_ offset [7:0] ch0_sync_offset 0x00 r/w 0x00a ch1_sync_ offset [7:0] ch1_sync_offset 0x00 r/w 0x00b ch2_sync_ offset [7:0] ch2_sync_offset 0x00 r/w 0x00c ch3_sync_ offset [7:0] ch3_sync_offset 0x00 r/w 0x00d ch4_sync_ offset [7:0] ch4_sync_offset 0x00 r/w 0x00e ch5_sync_ offset [7:0] ch5_sync_offset 0x00 r/w 0x00f ch6_sync_ offset [7:0] ch6_sync_offset 0x00 r/w 0x010 ch7_sync_ offset [7:0] ch7_sync_offset 0x00 r/w 0x011 general_ user_ config_1 [7:0] all_ ch_dis_ mclk_ en power- mode pdb_vcm pdb_ refout_ buf pdb_ sar pdb_ rc_osc soft_reset 0x24 r/w 0x012 general_ user_ config_2 [7:0] reserved sar_diag_ mode_en sdo_drive_str dout_drive_str spi_sync 0x09 r/w 0x013 general_ user_ config_3 [7:0] convst_ deglitch_dis reserved spi_slave_ mode_en reserved clk_ qual_dis 0x80 r/w 0x014 dout_forma t [7:0] dout_format dout_ header_ format reserved dclk_clk_div reserved 0x20 r/w 0x015 adc_mux_ config [7:0] ref_mux_ctrl mtr_mux_ctrl reserved 0x00 r/w 0x016 global_mux_ config [7:0] global_mux_ctrl reserved 0x00 r/w 0x017 gpio_config [7:0] rese rved gpio_op_en 0x00 r/w 0x018 gpio_data [7:0] rese rved gpio_read_data gp io_write_data 0x00 r/w 0x019 buffer_ config_1 [7:0] reserved ref_buf_ pos_en ref_ buf_ neg_en reserved 0x38 r/w 0x01a buffer_ config_2 [7:0] ref- bufp_ preq ref- bufn_ preq reserved pdb_aldo 1_ovrdrv pdb_ aldo2_ ovrdrv pdb_ dldo_ ovrdrv 0xc0 r/w
AD7779 data sheet rev. 0 | page 58 of 97 reg. name bits bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x01c ch0_offset_ upper_byte [7:0] ch0_offset_all[23:16] 0x00 r/w 0x01d ch0_offset_ mid_byte [7:0] ch0_offset_all[15:8] 0x00 r/w 0x01e ch0_offset_ lower_byte [7:0] ch0_offset_all[7:0] 0x00 r/w 0x01f ch0_gain_ upper_byte [7:0] ch0_gain_all[23:16] 0x00 r/w 0x020 ch0_gain_ mid_byte [7:0] ch0_gain_all[15:8] 0x00 r/w 0x021 ch0_gain_ lower_byte [7:0] ch0_gain_all[7:0] 0x00 r/w 0x022 ch1_offset_ upper_byte [7:0] ch1_offset_all[23:16] 0x00 r/w 0x023 ch1_offset_ mid_byte [7:0] ch1_offset_all[15:8] 0x00 r/w 0x024 ch1_offset_ lower_byte [7:0] ch1_offset_all[7:0] 0x00 r/w 0x025 ch1_gain_ upper_byte [7:0] ch1_gain_all[23:16] 0x00 r/w 0x026 ch1_gain_ mid_byte [7:0] ch1_gain_all[15:8] 0x00 r/w 0x027 ch1_gain_ lower_byte [7:0] ch1_gain_all[7:0] 0x00 r/w 0x028 ch2_offset_ upper_byte [7:0] ch2_offset_all[23:16] 0x00 r/w 0x029 ch2_offset_ mid_byte [7:0] ch2_offset_all[15:8] 0x00 r/w 0x02a ch2_offset_ lower_byte [7:0] ch2_offset_all[7:0] 0x00 r/w 0x02b ch2_gain_ upper_byte [7:0] ch2_gain_all[23:16] 0x00 r/w 0x02c ch2_gain_ mid_byte [7:0] ch2_gain_all[15:8] 0x00 r/w 0x02d ch2_gain_ lower_byte [7:0] ch2_gain_all[7:0] 0x00 r/w 0x02e ch3_offset_ upper_byte [7:0] ch3_offset_all[23:16] 0x00 r/w 0x02f ch3_offset_ mid_byte [7:0] ch3_offset_all[15:8] 0x00 r/w 0x030 ch3_offset_ lower_byte [7:0] ch3_offset_all[7:0] 0x00 r/w 0x031 ch3_gain_ upper_byte [7:0] ch3_gain_all[23:16] 0x00 r/w 0x032 ch3_gain_ mid_byte [7:0] ch3_gain_all[15:8] 0x00 r/w 0x033 ch3_gain_ lower_byte [7:0] ch3_gain_all[7:0] 0x00 r/w 0x034 ch4_offset_ upper_byte [7:0] ch4_offset_all[23:16] 0x00 r/w 0x035 ch4_offset_ mid_byte [7:0] ch4_offset_all[15:8] 0x00 r/w 0x036 ch4_offset_ lower_byte [7:0] ch4_offset_all[7:0] 0x00 r/w 0x037 ch4_gain_ upper_byte [7:0] ch4_gain_all[23:16] 0x00 r/w 0x038 ch4_gain_ mid_byte [7:0] ch4_gain_all[15:8] 0x00 r/w 0x039 ch4_gain_ lower_byte [7:0] ch4_gain_all[7:0] 0x00 r/w 0x03a ch5_offset_ upper_byte [7:0] ch5_offset_all[23:16] 0x00 r/w
data sheet AD7779 rev. 0 | page 59 of 97 reg. name bits bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x03b ch5_offset_ mid_byte [7:0] ch5_offset_all[15:8] 0x00 r/w 0x03c ch5_offset_ lower_byte [7:0] ch5_offset_all[7:0] 0x00 r/w 0x03d ch5_gain_ upper_byte [7:0] ch5_gain_all[23:16] 0x00 r/w 0x03e ch5_gain_ mid_byte [7:0] ch5_gain_all[15:8] 0x00 r/w 0x03f ch5_gain_ lower_byte [7:0] ch5_gain_all[7:0] 0x00 r/w 0x040 ch6_offset_ upper_byte [7:0] ch6_offset_all[23:16] 0x00 r/w 0x041 ch6_offset_ mid_byte [7:0] ch6_offset_all[15:8] 0x00 r/w 0x042 ch6_offset_ lower_byte [7:0] ch6_offset_all[7:0] 0x00 r/w 0x043 ch6_gain_ upper_byte [7:0] ch6_gain_all[23:16] 0x00 r/w 0x044 ch6_gain_ mid_byte [7:0] ch6_gain_all[15:8] 0x00 r/w 0x045 ch6_gain_ lower_byte [7:0] ch6_gain_all[7:0] 0x00 r/w 0x046 ch7_offset_ upper_byte [7:0] ch7_offset_all[23:16] 0x00 r/w 0x047 ch7_offset_ mid_byte [7:0] ch7_offset_all[15:8] 0x00 r/w 0x048 ch7_offset_ lower_byte [7:0] ch7_offset_all[7:0] 0x00 r/w 0x049 ch7_gain_ upper_byte [7:0] ch7_gain_all[23:16] 0x00 r/w 0x04a ch7_gain_ mid_byte [7:0] ch7_gain_all[15:8] 0x00 r/w 0x04b ch7_gain_ lower_byte [7:0] ch7_gain_all[7:0] 0x00 r/w 0x04c ch0_err_reg [7:0] reserved ch0_err_ ainm_uv ch0_ err_ ainm_ ov ch0_ err_ainp_ uv ch0_err_ ainp_ov ch0_err_ ref_det 0x00 r 0x04d ch1_err_reg [7:0] reserved ch1_err_ ainm_uv ch1_ err_ ainm_ ov ch1_ err_ainp_ uv ch1_err_ ainp_ov ch1_err_ ref_det 0x00 r 0x04e ch2_err_reg [7:0] reserved ch2_err_ ainm_uv ch2_ err_ ainm_ ov ch2_ err_ainp_ uv ch2_err_ ainp_ov ch2_err_ ref_det 0x00 r 0x04f ch3_err_reg [7:0] reserved ch3_err_ ainm_uv ch3_ err_ ainm_ ov ch3_ err_ainp_ uv ch3_err_ ainp_ov ch3_err_ ref_det 0x00 r 0x050 ch4_err_reg [7:0] reserved ch4_err_ ainm_uv ch4_er r_ ainm_o v ch4_ err_ainp_ uv ch4_err_a inp_ov ch4_err_ ref_det 0x00 r 0x051 ch5_err_reg [7:0] reserved ch5_err_ ainm_uv ch5_ err_ ainm_ ov ch5_ err_ainp_ uv ch5_err_ ainp_ov ch5_err_ ref_det 0x00 r 0x052 ch6_err_reg [7:0] reserved ch6_err_ ainm_uv ch6_ err_ ainm_ ov ch6_ err_ainp_ uv ch6_err_ ainp_ov ch6_err_ ref_det 0x00 r
AD7779 data sheet rev. 0 | page 60 of 97 reg. name bits bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x053 ch7_err_reg [7:0] reserved ch7_err_ ainm_uv ch7_ err_ ainm_ ov ch7_ err_ ainp_uv ch7_err_ ainp_ov ch7_err_ ref_det 0x00 r 0x054 ch0_1_sat_ err [7:0] reserved ch1_err_ mod_sat ch1_err_ filter_sat ch1_ err_ out- put_ sat ch0_err_ mod_sat ch0_err_ filter_sat ch0_err_ output_ sat 0x00 r 0x055 ch2_3_sat_ err [7:0] reserved ch3_err_ mod_sat ch3_err_ filter_sat ch3_ err_ out- put_ sat ch2_err_ mod_sat ch2_err_ filter_sat ch2_err_ output_ sat 0x00 r 0x056 ch4_5_sat_ err [7:0] reserved ch5_err_ mod_sat ch5_err_ filter_sat ch5_ err_ out- put_ sat ch4_err_ mod_sat ch4_err_ filter_sat ch4_err_ output_ sat 0x00 r 0x057 ch6_7_sat_ err [7:0] reserved ch7_err_ mod_sat ch7_err_ filter_sat ch7_ err_ out- put_ sat ch6_err_ mod_sat ch6_err_ filter_sat ch6_err_ output_ sat 0x00 r 0x058 chx_err_ reg_en [7:0] output_ sat_ test_ en filter_ sat_ test_en mod_sat_ test_en ainm_uv_ test_en ainm_ ov_ test_en ainp_uv_ test_en ainp_ov_ test_en ref_det_ test_en 0xfe r/w 0x059 gen_err_ reg_1 [7:0] reserv ed memmap_ crc_err rom_crc_ err spi_ clk_ count_ err spi_ invalid_ read_err spi_ invalid_ write_err spi_crc_ err 0x00 r 0x05a gen_err_ reg_1_en [7:0] reserv ed memmap_ crc_test_en rom_crc_ test_en spi_ clk_ count_ test_en spi_ invalid_ read_ test_en spi_ invalid_ write_ test_en spi_crc_ test_en 0x3e r/w 0x05b gen_err_ reg_2 [7:0] reserved reset_ detected ext_mclk_ switch_err re- served aldo1_ psm_err aldo2_ psm_err dldo_ psm_err 0x00 r 0x05c gen_err_ reg_2_en [7:0] reserved reset_ detect_en reserved ldo_psm_test_en ldo_psm_trip_test_en 0x3c r/w 0x05d status_reg_1 [7:0] reserved chip_error err_loc_ ch4 err_ loc_ ch3 err_ loc_ch2 err_loc_ ch1 err_loc_ ch0 0x00 r 0x05e status_reg_2 [7:0] reserved chip_error err_loc_ gen2 err_ loc_ gen1 err_ loc_ch7 err_loc_ ch6 err_loc_ ch5 0x00 r 0x05f status_reg_3 [7:0] reserved chip_error init_ complete err_ loc_ sat_ ch6_7 err_ loc_sat_ ch4_5 err_ loc_sat_ ch2_3 err_loc_ sat_ch0_1 0x00 r 0x060 src_n_msb [7:0] reserved src_n_all[11:8] 0x00 r/w 0x061 src_n_lsb [7:0] src_n_all[7:0] 0x80 r/w 0x062 src_if_msb [7:0] src_if_all[15:8] 0x00 r/w 0x063 src_if_lsb [7:0] src_if_all[7:0] 0x00 r/w 0x064 src_update [7:0] src_ load_ source reserved src_ load_ update 0x00 r/w
data sheet AD7779 rev. 0 | page 61 of 97 register details channel 0 configuration register address: 0x000, reset: 0x00, name: ch0_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor c h a n n e l me te r mu x r x mo d e 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch0_gain (r/w) [2:0] reserved [5] ch0_ref_monitor (r/w ) [3] reserved [4] ch0_rx (r/w) table 44. bit descriptions for ch0_config bits bit name settings description reset access [7:6] ch0_gain afe gain 0x0 r/w 00 gain 1 01 gain 2 10 gain 4 11 gain 8 5 ch0_ref_monitor channel used as reference monitor 0x0 r/w 4 ch0_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 1 configuration register address: 0x001, reset: 0x00, name: ch1_config a fe gain 11: gain = 8. 10: gain = 4. 01: gain = 2. 00: gain = 1. channel used as reference monitor c h a n n e l me te r mu x r x mo d e 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch1_gain (r/w ) [2:0] reserved [5] ch1_ref_monitor (r/w ) [3] reserved [4] ch1_rx (r/w) table 45. bit descriptions for ch1_config bits bit name settings description reset access [7:6] ch1_gain afe gain 0x0 r/w 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 8 5 ch1_ref_monitor channel used as reference monitor 0x0 r/w 4 ch1_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w
AD7779 data sheet rev. 0 | page 62 of 97 channel 2 configuration register address: 0x002, reset: 0x00, name: ch2_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor c h a n n e l me te r mu x r x mo d e 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch2_gain (r/w ) [2:0] reserved [5] ch2_ref_monitor (r/w ) [3] reserved [4] ch2_rx (r/w) table 46. bit descriptions for ch2_config bits bit name settings description reset access [7:6] ch2_gain afe gain 0x0 r/w 00 gain 1 01 gain 2 10 gain 4 11 gain 8 5 ch2_ref_monitor channel used as reference monitor 0x0 r/w 4 ch2_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 3 configuration register address: 0x003, reset: 0x00, name: ch3_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor c h a n n e l me te r mu x r x mo d e 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch3_gain (r/w ) [2:0] reserved [5] ch3_ref_monitor (r/w ) [3] reserved [4] ch3_rx (r/w) table 47. bit descriptions for ch3_config bits bit name settings description reset access [7:6] ch3_gain afe gain 0x0 r/w 00 gain 1 01 gain 2 10 gain 4 11 gain 8 5 ch3_ref_monitor channel used as reference monitor 0x0 r/w 4 ch3_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w
data sheet AD7779 rev. 0 | page 63 of 97 channel 4 configuration register address: 0x004, reset: 0x00, name: ch4_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor c h a n n e l me te r mu x r x mo d e 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch4_gain (r/w ) [2:0] reserved [5] ch4_ref_monitor (r/w ) [3] reserved [4] ch4_rx (r/w) table 48. bit descriptions for ch4_config bits bit name settings description reset access [7:6] ch4_gain afe gain 0x0 r/w 00 gain 1 01 gain 2 10 gain 4 11 gain 8 5 ch4_ref_monitor channel used as reference monitor 0x0 r/w 4 ch4_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 5 configuration register address: 0x005, reset: 0x00, name: ch5_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor c h a n n e l me te r mu x r x mo d e 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch5_gain (r/w ) [2:0] reserved [5] ch5_ref_monitor (r/w ) [3] reserved [4] ch5_rx (r/w) table 49. bit descriptions for ch5_config bits bit name settings description reset access [7:6] ch5_gain afe gain 0x0 r/w 00 gain 1 01 gain 2 10 gain 4 11 gain 8 5 ch5_ref_monitor channel used as reference monitor 0x0 r/w 4 ch5_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w
AD7779 data sheet rev. 0 | page 64 of 97 channel 6 configuration register address: 0x006, reset: 0x00, name: ch6_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor c h a n n e l me te r mu x r x mo d e 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch6_gain (r/w ) [2:0] reserved [5] ch6_ref_monitor (r/w ) [3] reserved [4] ch6_rx (r/w) table 50. bit descriptions for ch6_config bits bit name settings description reset access [7:6] ch6_gain afe gain 0x0 r/w 00 gain 1 01 gain 2 10 gain 4 11 gain 8 5 ch6_ref_monitor channel used as reference monitor 0x0 r/w 4 ch6_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 7 configuration register address: 0x007, reset: 0x00, name: ch7_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor c h a n n e l me te r mu x r x mo d e 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch7_gain (r/w ) [2:0] reserved [5] ch7_ref_monitor (r/w ) [3] reserved [4] ch7_rx (r/w) table 51. bit descriptions for ch7_config bits bit name settings description reset access [7:6] ch7_gain afe gain 0x0 r/w 00 gain 1 01 gain 2 10 gain 4 11 gain 8 5 ch7_ref_monitor channel used as reference monitor 0x0 r/w 4 ch7_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w
data sheet AD7779 rev. 0 | page 65 of 97 disable clocks to adc channel register address: 0x008, reset: 0x00, name: ch_disable channel 7 disable channel 0 disable channel 6 disable channel 1 disable channel 5 disable channel 2 disable channel 4 disable channel 3 disable 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7] ch7_disable (r/w ) [0] ch0_disable (r/w ) [6] ch6_disable (r/w ) [1] ch1_disable (r/w ) [5] ch5_disable (r/w ) [2] ch2_disable (r/w ) [4] ch4_disable (r/w ) [3] ch3_disable (r/w ) table 52. bit descriptions for ch_disable bits bit name settings description reset access 7 ch7_disable channel 7 disable 0x0 r/w 6 ch6_disable channel 6 disable 0x0 r/w 5 ch5_disable channel 5 disable 0x0 r/w 4 ch4_disable channel 4 disable 0x0 r/w 3 ch3_disable channel 3 disable 0x0 r/w 2 ch2_disable channel 2 disable 0x0 r/w 1 ch1_disable channel 1 disable 0x0 r/w 0 ch0_disable channel 0 disable 0x0 r/w channel 0 sync offset register address: 0x009, reset: 0x00, name: ch0_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_sync_offset (r/w ) table 53. bit descriptions for ch0_sync_offset bits bit name settings description reset access [7:0] ch0_sync_offset channel sync offset 0x0 r/w channel 1 sync offset register address: 0x00a, reset: 0x00, name: ch1_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_sync_offset (r/w ) table 54. bit descriptions for ch1_sync_offset bits bit name settings description reset access [7:0] ch1_sync_offset channel sync offset 0x0 r/w
AD7779 data sheet rev. 0 | page 66 of 97 channel 2 sync offset register address: 0x00b, reset: 0x00, name: ch2_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_sync_offset (r/w ) table 55. bit descriptions for ch2_sync_offset bits bit name settings description reset access [7:0] ch2_sync_offset channel sync offset 0x0 r/w channel 3 sync offset register address: 0x00c, reset: 0x00, name: ch3_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_sync_offset (r/w ) table 56. bit descriptions for ch3_sync_offset bits bit name settings description reset access [7:0] ch3_sync_offset channel sync offset 0x0 r/w channel 4 sync offset register address: 0x00d, reset: 0x00, name: ch4_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_sync_offset (r/w ) table 57. bit descriptions for ch4_sync_offset bits bit name settings description reset access [7:0] ch4_sync_offset channel sync offset 0x0 r/w channel 5 sync offset register address: 0x00e, reset: 0x00, name: ch5_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_sync_offset (r/w ) table 58. bit descriptions for ch5_sync_offset bits bit name settings description reset access [7:0] ch5_sync_offset channel sync offset 0x0 r/w
data sheet AD7779 rev. 0 | page 67 of 97 channel 6 sync offset register address: 0x00f, reset: 0x00, name: ch6_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_sync_offset (r/w ) table 59. bit descriptions for ch6_sync_offset bits bit name settings description reset access [7:0] ch6_sync_offset channel sync offset 0x0 r/w channel 7 sync offset register address: 0x010, reset: 0x00, name: ch7_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_sync_offset (r/w ) table 60. bit descriptions for ch7_sync_offset bits bit name settings description reset access [7:0] ch7_sync_offset channel sync offset 0x0 r/w general user configuration 1 register address: 0x011, reset: 0x24, name: general_user_config_1 if all sd channels are disabled, setting this bit high allows dclk to continue toggling soft res et 11: 1st write. 10: 2nd write. 01: no effect. 00: no effect. power mode 1: high resolution. 0: low power (1/4) powerdown signal for internal oscillator . active low powerdown vcm buffer. active low powerdown sa. active low powerdown internal reference output buffer. active low 0 0 1 0 2 1 3 0 4 0 5 1 6 0 7 0 [7] all_ch_dis__mclk_en (r/w) [1:0] soft_reset (r/w) [6] powermode (r/w) [2] pdb_rc_osc (r/w ) [5] pdb_vcm (r/w) [3] pdb_sar (r/w) [4] pdb_refout_buf (r/w ) table 61. bit descriptions for general_user_config_1 bits bit name settings description reset access 7 all_ch_dis_mclk_en if all - channels are disabled, setting this bit high allows dclk to continue toggling. 0x0 r/w 6 powermode power mode. 0x0 r/w 0 low power (1/4). 1 high resolution. 5 pdb_vcm power down vcm buffer. active low. 0x1 r/w 4 pdb_refout_buf power down internal reference output buffer. active low. 0x0 r/w 3 pdb_sar power down sar. active low. 0x0 r/w 2 pdb_rc_osc power down signal for internal oscillator. active low. 0x1 r/w
AD7779 data sheet rev. 0 | page 68 of 97 bits bit name settings description reset access [1:0] soft_reset soft reset 0x0 r/w 00 no effect 01 no effect 10 2nd write 11 1st write general user configuration 2 register address: 0x012, reset: 0x09, name: general_user_config_2 sync pulse generated thru spi 1: startb pin in the control module. this bit is anded with the value on 0: generate a puls e in /sync_in pin. on startb pin in the control module , this signal is anded with the value dout drive strength 11: extra strong. 10: weak. 01: strong. 00: nominal. sets spi interface to read back sar result on sdo sdo drive strength 11: extra strong. 10: weak. 01: strong. 00: nominal. 0 1 1 0 2 0 3 1 4 0 5 0 6 0 7 0 [7] reserved [0] spi_sync (r/w) [6] reserved [2:1] dout_drive_str (r/w ) [5] sar_diag_mode_en (r/w ) [4:3] sdo_drive_str (r/w) table 62. bit descriptions for general_user_config_2 bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w 5 sar_diag_mode_en sets spi interface to read back sar result on sdo. 0x0 r/w [4:3] sdo_drive_str sdo drive strength. 0x1 r/w 00 nominal. 01 strong. 10 weak. 11 extra strong. [2:1] dout_drive_str doutx drive strength. 0x0 r/w 00 nominal. 01 strong. 10 weak. 11 extra strong. 0 spi_sync sync pulse generated through spi. 0x1 r/w 0 this signal is anded with the value on the start pin in the control module and generates a pulse in the sync_in pin. 1 this bit is anded with the value on start pin in the control module.
data sheet AD7779 rev. 0 | page 69 of 97 general user configuration 3 register address: 0x013, reset: 0x80, name: general_user_config_3 disable deglitching of convst pin 11: no deglitch circuit. 10: convst_sar deglitch 1.5 mclk. 01: reserved. 00: reserved. disables the clock qualifier check if the user requires to use an mclk signal < 265khz. enable to spi slave mode to read back adc on sdo 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 [7:6] convst_deglitch_dis (r/w ) [0] clk_qual_dis (r/w ) [5] reserved [1] reserved [4] spi_slave_mode_en (r/w) [3:2] reserved table 63. bit descriptions for general_user_config_3 bits bit name settings description reset access [7:6] convst_deglitch_dis disable deglitching of convst _ sar pin 0x2 r/w 00 reserved. 01 reserved. 10 convst_sar deglitch 1.5 mclk. 11 no deglitch circuit. 5 reserved reserved. 0x0 r/w 4 spi_slave_mode_en enable to spi slave mode to read back adc on sdo 0x0 r/w [3:2] reserved reserved. 0x0 r/w 1 reserved reserved. 0x0 r/w 0 clk_qual_dis disables the clock qualifier check if the user requires to use an mclk signal <265 khz. 0x0 r/w data output format register address: 0x014, reset: 0x20, name: dout_format data out form at 11: 1 dout lines. 10: 1 dout lines. 01: 2 dout lines. 00: 4 dout lines. dout header format 1: crc header. 0: status header. divide mclk 111: divide by 128. 110: divide by 64. 101: divide by 32. 100: divide by 16. 011: divide by 8. 010: divide by 4. 001: divide by 2. 000: divide by 1. 0 0 1 0 2 0 3 0 4 0 5 1 6 0 7 0 [7:6] dout_format (r/w) [0] reserved [5] dout_header_format (r/w ) [3:1] dclk_clk_div (r/w ) [4] reserved table 64. bit descriptions for dout_format bits bit name settings description reset access [7:6] dout_format data out format. 0x0 r/w 00 4 dout lines 01 2 dout lines 10 1 dout lines 11 1 dout lines
AD7779 data sheet rev. 0 | page 70 of 97 bits bit name settings description reset access 5 dout_header_format dout header format 0x1 r/w 0 status header 1 crc header 4 reserved reserved. 0x0 r/w [3:1] dclk_clk_div divide mclk 0x0 r/w 000 divide by 1 001 divide by 2 010 divide by 4 011 divide by 8 100 divide by 16 101 divide by 32 110 divide by 64 111 divide by 128 0 reserved reserved. 0x0 r/w main adc meter and reference mux control register address: 0x015, reset: 0x00, name: adc_mux_config sd adc reference mux 11: external reference refx-/refx+. 10: external supply avdd1x/avssx. 01: internal reference. 00: external reference refx+/refx- sd ad c me te r mu x 1001: external reference refx+/refx+. 1000: internal reference +/+. 0111: internal reference -/+. 0110: internal reference +/- 0101: external reference refx-/refx- 0100: external reference refx-/refx+. 0011: external reference refx+/refx- 0010: 280mv. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ref_mux_ctrl (r/w ) [1:0] reserved [5:2] mtr_mux_ctrl (r/w) table 65. bit descriptions for adc_mux_config bits bit name settings description reset access [7:6] ref_mux_ctrl sd adc reference mux 0x0 r/w 00 external reference refx+/refx? 01 internal reference. 10 external supply avdd1x/avssx. 11 external reference refx?/refx+. [5:2] mtr_mux_ctrl sd adc meter mux 0x0 r/w 0010 280 mv 0011 external reference refx+/refx? 0100 external reference refx?/refx+ 0101 external reference refx?/refx? 0110 internal reference +/? 0111 internal reference ?/+
data sheet AD7779 rev. 0 | page 71 of 97 bits bit name settings description reset access 1000 internal reference +/+ 1001 external reference refx+/refx+ [1:0] reserved reserved. 0x0 r/w global diagnostics mux register address: 0x016, reset: 0x00, name: global_mux_config global sar diagnostics mux control 10101: avssx avdd4. attenuated. 10100: ref2+ avssx. 10011: ref1+ avssx. ... 00010: ref1p ref1n. 00001: dvbe avssx. 00000: auxain+ auxain- 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:3] global_mux_ctrl (r/w) [2:0] reserved table 66. bit descriptions for global_mux_config bits bit name settings description reset access [7:3] global_mux_ctrl global sar diagnostics mux control. 0x0 r/w 00000 auxain+/auxain?. 00001 dv be /avssx. 00010 ref1+/ref1?. 10011 ref2+/ref2?. 10100 ref_out/avssx. 10101 vcm/avssx. 10110 areg1cap/avssx. 10111 areg2cap/avssx. 11000 dregcap/dgnd. 11001 avdd1a/avssx. 11010 avdd1b/avssx. 11011 avdd2a/avssx. 11100 avdd2b/avssx. 11101 iovdd/dgnd. 11110 avdd4/avssx. 11111 dgnd/avss1a. 10000 dgnd/avss1b. 10001 dgnd/avssx. 10010 avdd4/avssx. 10011 ref1+/avssx. 10100 ref2+/avssx. 10101 avdd4/avssx. attenuated. [2:0] reserved reserved. 0x0 r/w
AD7779 data sheet rev. 0 | page 72 of 97 gpio configuration register address: 0x017, reset: 0x00, name: gpio_config gpio input/output 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:3] reserved [2:0] gpio_op_en (r/w) table 67. bit descriptions for gpio_config bits bit name settings description reset access [7:3] reserved reserved. 0x0 r/w [2:0] gpio_op_en gpio input/output 0x0 r/w gpio data register address: 0x018, reset: 0x00, name: gpio_data value sent to gpio pins data read from gpio pins 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [2:0] gpio_write_data (r/w ) [5:3] gpio_read_data (r) table 68. bit descriptions for gpio_data bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w [5:3] gpio_read_data data read from the gpio pins 0x0 r [2:0] gpio_write_data value sent to the gpio pins 0x0 r/w buffer configuration 1 register address: 0x019, reset: 0x38, name: buffer_config_1 reference buffer positive enable reference buffer negative enable 0 0 1 0 2 0 3 1 4 1 5 0 6 0 7 0 [7] reserved [0] reserved [6] reserved [1] reserved [5] reserved [2] reserved [ 4 ] ref_ buf_ p os _ en ( r/w ) [ 3 ] ref_ buf_ neg_ en ( r/w ) table 69. bit descriptions for buffer_config_1 bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ref_buf_pos_en reference buffer positive enable 0x1 r/w 3 ref_buf_neg_en reference buffer negative enable 0x1 r/w [2:0] reserved reserved 0x0 r/w
data sheet AD7779 rev. 0 | page 73 of 97 buffer configuration 2 register address: 0x01a, reset: 0xc0, name: buffer_config_2 reference buffer positive precharge enable dregcap overdrive enable. reference buffer negative precharge enable areg2cap overdrive enable areg1cap overdrive enable 0 0 1 0 2 0 3 0 4 0 5 0 6 1 7 1 [7] refbufp_preq (r/w ) [0] pdb_dldo_ovrdrv (r/w ) [6] refbufn_preq (r/w ) [1] pdb_aldo2_ovrdrv (r/w ) [5:3] reserved [2] pdb_aldo1_ovrdrv (r/w ) table 70. bit descriptions for buffer_config_2 bits bit name settings description reset access 7 refbufp_preq reference buffer positive precharge enable 0x1 r/w 6 refbufn_preq reference buffer negative precharge enable 0x1 r/w [5:3] reserved reserved. 0x0 r/w 2 pdb_aldo1_ovrdrv areg1cap overdrive enable 0x0 r/w 1 pdb_aldo2_ovrdrv areg2cap overdrive enable 0x0 r/w 0 pdb_dldo_ovrdrv dregcap overdrive enable 0x0 r/w channel 0 offset upper byte register address: 0x01c, reset: 0x00, name: ch0_offset_upper_byte combined offset register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_offset_all[23:16] (r/w) table 71. bit descriptions for ch0_offset_upper_byte bits bit name settings description reset access [7:0] ch0_offset_all[23:16] combined offset register channel 0 0x0 r/w channel 0 offset middle byte register address: 0x01d, reset: 0x00, name: ch0_offset_mid_byte combined offset register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_offset_all[15:8] (r/w) table 72. bit descriptions for ch0_offset_mid_byte bits bit name settings description reset access [7:0] ch0_offset_all[15:8] combined offset register channel 0 0x0 r/w
AD7779 data sheet rev. 0 | page 74 of 97 channel 0 offset lower byte register address: 0x01e, reset: 0x00, name: ch0_offset_lower_byte combined offset register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_offset_all[7:0] (r/w) table 73. bit descriptions for ch0_offset_lower_byte bits bit name settings description reset access [7:0] ch0_offset_all[7:0] combined offset register channel 0 0x0 r/w channel 0 gain upper byte register address: 0x01f, reset: 0x00, name: ch0_gain_upper_byte combined gain register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_gain_all[23:16] (r/w) table 74. bit descriptions for ch0_gain_upper_byte bits bit name settings description reset access [7:0] ch0_gain_all[23:16] combined gain register channel 0 0x0 r/w channel 0 gain middle byte register address: 0x020, reset: 0x00, name: ch0_gain_mid_byte combined gain register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_gain_all[15:8] (r/w) table 75. bit descriptions for ch0_gain_mid_byte bits bit name settings description reset access [7:0] ch0_gain_all[15:8] combined gain register channel 0 0x0 r/w channel 0 gain lower byte register address: 0x021, reset: 0x00, name: ch0_gain_lower_byte combined gain register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_gain_all[7:0] (r/w ) table 76. bit descriptions for ch0_gain_lower_byte bits bit name settings description reset access [7:0] ch0_gain_all[7:0] combined gain register channel 0 0x0 r/w
data sheet AD7779 rev. 0 | page 75 of 97 channel 1 offset upper byte register address: 0x022, reset: 0x00, name: ch1_offset_upper_byte combined offset register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_offset_all[23:16] (r/w) table 77. bit descriptions for ch1_offset_upper_byte bits bit name settings description reset access [7:0] ch1_offset_all[23:16] combined offset register channel 1 0x0 r/w channel 1 offset middle byte register address: 0x023, reset: 0x00, name: ch1_offset_mid_byte combined offset register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_offset_all[15:8] (r/w) table 78. bit descriptions for ch1_offset_mid_byte bits bit name settings description reset access [7:0] ch1_offset_all[15:8] combined offset register channel 1 0x0 r/w channel 1 offset lower byte register address: 0x024, reset: 0x00, name: ch1_offset_lower_byte combined offset register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_offset_all[7:0] (r/w) table 79. bit descriptions for ch1_offset_lower_byte bits bit name settings description reset access [7:0] ch1_offset_all[7:0] combined offset register channel 1 0x0 r/w channel 1 gain upper byte register address: 0x025, reset: 0x00, name: ch1_gain_upper_byte combined gain register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_gain_all[23:16] (r/w) table 80. bit descriptions for ch1_gain_upper_byte bits bit name settings description reset access [7:0] ch1_gain_all[23:16] combined gain register channel 1 0x0 r/w
AD7779 data sheet rev. 0 | page 76 of 97 channel 1 gain middle byte register address: 0x026, reset: 0x00, name: ch1_gain_mid_byte combined gain register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_gain_all[15:8] (r/w) table 81. bit descriptions for ch1_gain_mid_byte bits bit name settings description reset access [7:0] ch1_gain_all[15:8] combined gain register channel 1 0x0 r/w channel 1 gain lower byte register address: 0x027, reset: 0x00, name: ch1_gain_lower_byte combined gain register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_gain_all[7:0] (r/w ) table 82. bit descriptions for ch1_gain_lower_byte bits bit name settings description reset access [7:0] ch1_gain_all[7:0] combined gain register channel 1 0x0 r/w channel 2 offset upper byte register address: 0x028, reset: 0x00, name: ch2_offset_upper_byte combined offset register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_offset_all[23:16] (r/w) table 83. bit descriptions for ch2_offset_upper_byte bits bit name settings description reset access [7:0] ch2_offset_all[23:16] combined offset register channel 2 0x0 r/w channel 2 offset middle byte register address: 0x029, reset: 0x00, name: ch2_offset_mid_byte combined offset register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_offset_all[15:8] (r/w) table 84. bit descriptions for ch2_offset_mid_byte bits bit name settings description reset access [7:0] ch2_offset_all[15:8] combined offset register channel 2 0x0 r/w
data sheet AD7779 rev. 0 | page 77 of 97 channel 2 offset lower byte register address: 0x02a, reset: 0x00, name: ch2_offset_lower_byte combined offset register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_offset_all[7:0] (r/w) table 85. bit descriptions for ch2_offset_lower_byte bits bit name settings description reset access [7:0] ch2_offset_all[7:0] combined offset register channel 2 0x0 r/w channel 2 gain upper byte register address: 0x02b, reset: 0x00, name: ch2_gain_upper_byte combined gain register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_gain_all[23:16] (r/w) table 86. bit descriptions for ch2_gain_upper_byte bits bit name settings description reset access [7:0] ch2_gain_all[23:16] combined gain register channel 2 0x0 r/w channel 2 gain middle byte register address: 0x02c, reset: 0x00, name: ch2_gain_mid_byte combined gain register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_gain_all[15:8] (r/w) table 87. bit descriptions for ch2_gain_mid_byte bits bit name settings description reset access [7:0] ch2_gain_all[15:8] combined gain register channel 2 0x0 r/w channel 2 gain lower byte register address: 0x02d, reset: 0x00, name: ch2_gain_lower_byte combined gain register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_gain_all[7:0] (r/w ) table 88. bit descriptions for ch2_gain_lower_byte bits bit name settings description reset access [7:0] ch2_gain_all[7:0] combined gain register channel 2 0x0 r/w
AD7779 data sheet rev. 0 | page 78 of 97 channel 3 offset upper byte register address: 0x02e, reset: 0x00, name: ch3_offset_upper_byte combined offset register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_offset_all[23:16] (r/w) table 89. bit descriptions for ch3_offset_upper_byte bits bit name settings description reset access [7:0] ch3_offset_all[23:16] combined offset register channel 3 0x0 r/w channel 3 offset middle byte register address: 0x02f, reset: 0x00, name: ch3_offset_mid_byte combined offset register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_offset_all[15:8] (r/w) table 90. bit descriptions for ch3_offset_mid_byte bits bit name settings description reset access [7:0] ch3_offset_all[15:8] combined offset register channel 3 0x0 r/w channel 3 offset lower byte register address: 0x030, reset: 0x00, name: ch3_offset_lower_byte combined offset register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_offset_all[7:0] (r/w) table 91. bit descriptions for ch3_offset_lower_byte bits bit name settings description reset access [7:0] ch3_offset_all[7:0] combined offset register channel 3 0x0 r/w channel 3 gain upper byte register address: 0x031, reset: 0x00, name: ch3_gain_upper_byte combined gain register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_gain_all[23:16] (r/w) table 92. bit descriptions for ch3_gain_upper_byte bits bit name settings description reset access [7:0] ch3_gain_all[23:16] combined gain register channel 3 0x0 r/w
data sheet AD7779 rev. 0 | page 79 of 97 channel 3 gain middle byte register address: 0x032, reset: 0x00, name: ch3_gain_mid_byte combined gain register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_gain_all[15:8] (r/w) table 93. bit descriptions for ch3_gain_mid_byte bits bit name settings description reset access [7:0] ch3_gain_all[15:8] combined gain register channel 3 0x0 r/w channel 3 gain lower byte register address: 0x033, reset: 0x00, name: ch3_gain_lower_byte combined gain register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_gain_all[7:0] (r/w ) table 94. bit descriptions for ch3_gain_lower_byte bits bit name settings description reset access [7:0] ch3_gain_all[7:0] combined gain register channel 3 0x0 r/w channel 4 offset upper byte register address: 0x034, reset: 0x00, name: ch4_offset_upper_byte combined offset register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_offset_all[23:16] (r/w) table 95. bit descriptions for ch4_offset_upper_byte bits bit name settings description reset access [7:0] ch4_offset_all[23:16] combined offset register channel 4 0x0 r/w channel 4 offset middle byte register address: 0x035, reset: 0x00, name: ch4_offset_mid_byte combined offset register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_offset_all[15:8] (r/w) table 96. bit descriptions for ch4_offset_mid_byte bits bit name settings description reset access [7:0] ch4_offset_all[15:8] combined offset register channel 4 0x0 r/w
AD7779 data sheet rev. 0 | page 80 of 97 channel 4 offset lower byte register address: 0x036, reset: 0x00, name: ch4_offset_lower_byte combined offset register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_offset_all[7:0] (r/w) table 97. bit descriptions for ch4_offset_lower_byte bits bit name settings description reset access [7:0] ch4_offset_all[7:0] combined offset register channel 4 0x0 r/w channel 4 gain upper byte register address: 0x037, reset: 0x00, name: ch4_gain_upper_byte combined gain register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_gain_all[23:16] (r/w) table 98. bit descriptions for ch4_gain_upper_byte bits bit name settings description reset access [7:0] ch4_gain_all[23:16] combined gain register channel 4 0x0 r/w channel 4 gain middle byte register address: 0x038, reset: 0x00, name: ch4_gain_mid_byte combined gain register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_gain_all[15:8] (r/w) table 99. bit descriptions for ch4_gain_mid_byte bits bit name settings description reset access [7:0] ch4_gain_all[15:8] combined gain register channel 4 0x0 r/w channel 4 gain lower byte register address: 0x039, reset: 0x00, name: ch4_gain_lower_byte combined gain register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_gain_all[7:0] (r/w ) table 100. bit descriptions for ch4_gain_lower_byte bits bit name settings description reset access [7:0] ch4_gain_all[7:0] combined gain register channel 4 0x0 r/w
data sheet AD7779 rev. 0 | page 81 of 97 channel 5 offset upper byte register address: 0x03a, reset: 0x00, name: ch5_offset_upper_byte combined offset register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_offset_all[23:16] (r/w) table 101. bit descriptions for ch5_offset_upper_byte bits bit name settings description reset access [7:0] ch5_offset_all[23:16] combined offset register channel 5 0x0 r/w channel 5 offset middle byte register address: 0x03b, reset: 0x00, name: ch5_offset_mid_byte combined offset register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_offset_all[15:8] (r/w) table 102. bit descriptions for ch5_offset_mid_byte bits bit name settings description reset access [7:0] ch5_offset_all[15:8] combined offset register channel 5 0x0 r/w channel 5 offset lower byte register address: 0x03c, reset: 0x00, name: ch5_offset_lower_byte combined offset register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_offset_all[7:0] (r/w) table 103. bit descriptions for ch5_offset_lower_byte bits bit name settings description reset access [7:0] ch5_offset_all[7:0] combined offset register channel 5 0x0 r/w channel 5 gain upper byte register address: 0x03d, reset: 0x00, name: ch5_gain_upper_byte combined gain register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_gain_all[23:16] (r/w) table 104. bit descriptions for ch5_gain_upper_byte bits bit name settings description reset access [7:0] ch5_gain_all[23:16] combined gain register channel 5 0x0 r/w
AD7779 data sheet rev. 0 | page 82 of 97 channel 5 gain middle byte register address: 0x03e, reset: 0x00, name: ch5_gain_mid_byte combined gain register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_gain_all[15:8] (r/w) table 105. bit descriptions for ch5_gain_mid_byte bits bit name settings description reset access [7:0] ch5_gain_all[15:8] combined gain register channel 5 0x0 r/w channel 5 gain lower byte register address: 0x03f, reset: 0x00, name: ch5_gain_lower_byte combined gain register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_gain_all[7:0] (r/w ) table 106. bit descriptions for ch5_gain_lower_byte bits bit name settings description reset access [7:0] ch5_gain_all[7:0] combined gain register channel 5 0x0 r/w channel 6 offset upper byte register address: 0x040, reset: 0x00, name: ch6_offset_upper_byte combined offset register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_offset_all[23:16] (r/w) table 107. bit descriptions for ch6_offset_upper_byte bits bit name settings description reset access [7:0] ch6_offset_all[23:16] combined offset register channel 6 0x0 r/w channel 6 offset middle byte register address: 0x041, reset: 0x00, name: ch6_offset_mid_byte combined offset register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_offset_all[15:8] (r/w) table 108. bit descriptions for ch6_offset_mid_byte bits bit name settings description reset access [7:0] ch6_offset_all[15:8] combined offset register channel 6 0x0 r/w
data sheet AD7779 rev. 0 | page 83 of 97 channel 6 offset lower byte register address: 0x042, reset: 0x00, name: ch6_offset_lower_byte combined offset register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_offset_all[7:0] (r/w) table 109. bit descriptions for ch6_offset_lower_byte bits bit name settings description reset access [7:0] ch6_offset_all[7:0] combined offset register channel 6 0x0 r/w channel 6 gain upper byte register address: 0x043, reset: 0x00, name: ch6_gain_upper_byte combined gain register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_gain_all[23:16] (r/w) table 110. bit descriptions for ch6_gain_upper_byte bits bit name settings description reset access [7:0] ch6_gain_all[23:16] combined gain register channel 6 0x0 r/w channel 6 gain middle byte register address: 0x044, reset: 0x00, name: ch6_gain_mid_byte combined gain register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_gain_all[15:8] (r/w) table 111. bit descriptions for ch6_gain_mid_byte bits bit name settings description reset access [7:0] ch6_gain_all[15:8] combined gain register channel 6 0x0 r/w channel 6 gain lower byte register address: 0x045, reset: 0x00, name: ch6_gain_lower_byte combined gain register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_gain_all[7:0] (r/w ) table 112. bit descriptions for ch6_gain_lower_byte bits bit name settings description reset access [7:0] ch6_gain_all[7:0] combined gain register channel 6 0x0 r/w
AD7779 data sheet rev. 0 | page 84 of 97 channel 7 offset upper byte register address: 0x046, reset: 0x00, name: ch7_offset_upper_byte combined offset register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_offset_all[23:16] (r/w) table 113. bit descriptions for ch7_offset_upper_byte bits bit name settings description reset access [7:0] ch7_offset_all[23:16] combined offset register channel 7 0x0 r/w channel 7 offset middle byte register address: 0x047, reset: 0x00, name: ch7_offset_mid_byte combined offset register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_offset_all[15:8] (r/w) table 114. bit descriptions for ch7_offset_mid_byte bits bit name settings description reset access [7:0] ch7_offset_all[15:8] combined offset register channel 7 0x0 r/w channel 7 offset lower byte register address: 0x048, reset: 0x00, name: ch7_offset_lower_byte combined offset register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_offset_all[7:0] (r/w) table 115. bit descriptions for ch7_offset_lower_byte bits bit name settings description reset access [7:0] ch7_offset_all[7:0] combined offset register channel 7 0x0 r/w channel 7 gain upper byte register address: 0x049, reset: 0x00, name: ch7_gain_upper_byte combined gain register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_gain all[23:16] (r/w) table 116. bit descriptions for ch7_gain_upper_byte bits bit name settings description reset access [7:0] ch7_gain all[23:16] combined gain register channel 7 0x0 r/w
data sheet AD7779 rev. 0 | page 85 of 97 channel 7 gain middle byte register address: 0x04a, reset: 0x00, name: ch7_gain_mid_byte combined gain register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_gain all[15:8] (r/w) table 117. bit descriptions for ch7_gain_mid_byte bits bit name settings description reset access [7:0] ch7_gain all[15:8] combined gain register channel 7 0x0 r/w channel 7 gain lower byte register address: 0x04b, reset: 0x00, name: ch7_gain_lower_byte combined gain register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_gain all[7:0] (r/w ) table 118. bit descriptions for ch7_gain_lower_byte bits bit name settings description reset access [7:0] ch7_gain all[7:0] combined gain register channel 7 0x0 r/w channel 0 status register address: 0x04c, reset: 0x00, name: ch0_err_reg channel 0 - reference detect erro r a in0- undervoltage error ain0+ overvoltage error a in0- overvoltage error ain0+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch0_err_ref_det (r) [4] ch0_err_ainm_uv (r) [1] ch0_err_ainp_ov (r) [3] ch0_err_ainm_ov (r) [2] ch0_err_ainp_uv (r) table 119. bit descriptions for ch0_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch0_err_ainm_uv channel 0ain0? undervoltage error 0x0 r 3 ch0_err_ainm_ov channel 0ain0? overvoltage error 0x0 r 2 ch0_err_ainp_uv channel 0ain0+ undervoltage error 0x0 r 1 ch0_err_ainp_ov channel 0ain0+ overvoltage error 0x0 r 0 ch0_err_ref_det channel 0reference detect error 0x0 r
AD7779 data sheet rev. 0 | page 86 of 97 channel 1 status register address: 0x04d, reset: 0x00, name: ch1_err_reg channel 1 - reference detect erro r a in1- undervoltage error ain1+ overvoltage error a in1- overvoltage error ain1+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch1_err_ref_det (r) [4] ch1_err_ainm_uv (r) [1] ch1_err_ainp_ov (r) [3] ch1_err_ainm_ov (r) [2] ch1_err_ainp_uv (r) table 120. bit descriptions for ch1_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch1_err_ainm_uv channel 1ain1? undervoltage error 0x0 r 3 ch1_err_ainm_ov channel 1ain1? overvoltage error 0x0 r 2 ch1_err_ainp_uv channel 1ain1+ undervoltage error 0x0 r 1 ch1_err_ainp_ov channel 1ain1+ overvoltage error 0x0 r 0 ch1_err_ref_det channel 1reference detect error 0x0 r channel 2 status register address: 0x04e, reset: 0x00, name: ch2_err_reg channel 2 - reference detect erro r a in2- undervoltage error ain2+ overvoltage error a in2- overvoltage error ain2+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch2_err_ref_det (r) [4] ch2_err_ainm_uv (r) [1] ch2_err_ainp_ov (r) [3] ch2_err_ainm_ov (r) [2] ch2_err_ainp_uv (r) table 121. bit descriptions for ch2_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch2_err_ainm_uv channel 2ain2? undervoltage error 0x0 r 3 ch2_err_ainm_ov channel 2ain2? overvoltage error 0x0 r 2 ch2_err_ainp_uv channel 2ain2+ undervoltage error 0x0 r 1 ch2_err_ainp_ov channel 2ain2+ overvoltage error 0x0 r 0 ch2_err_ref_det channel 2reference detect error 0x0 r
data sheet AD7779 rev. 0 | page 87 of 97 channel 3 status register address: 0x04f, reset: 0x00, name: ch3_err_reg channel 3 - reference detect erro r a in3- undervoltage error ain3+ overvoltage error a in3- overvoltage error ain3+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch3_err_ref_det (r) [4] ch3_err_ainm_uv (r) [1] ch3_err_ainp_ov (r) [3] ch3_err_ainm_ov (r) [2] ch3_err_ainp_uv (r) table 122. bit descriptions for ch3_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch3_err_ainm_uv channel 3ain3? undervoltage error 0x0 r 3 ch3_err_ainm_ov channel 3ain3? overvoltage error 0x0 r 2 ch3_err_ainp_uv channel 3ain3+ undervoltage error 0x0 r 1 ch3_err_ainp_ov channel 3ain3+ overvoltage error 0x0 r 0 ch3_err_ref_det channel 3reference detect error 0x0 r channel 4 status register address: 0x050, reset: 0x00, name: ch4_err_reg channel 4 - reference detect erro r a in4- undervoltage error ain4+ overvoltage error a in4- overvoltage error ain4+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch4_err_ref_det (r) [4] ch4_err_ainm_uv (r) [1] ch4_err_ainp_ov (r) [3] ch4_err_ainm_ov (r) [2] ch4_err_ainp_uv (r) table 123. bit descriptions for ch4_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch4_err_ainm_uv channel 4ain4? undervoltage error 0x0 r 3 ch4_err_ainm_ov channel 4ain4? overvoltage error 0x0 r 2 ch4_err_ainp_uv channel 4ain4+ undervoltage error 0x0 r 1 ch4_err_ainp_ov channel 4ain4+ overvoltage error 0x0 r 0 ch4_err_ref_det channel 4reference detect error 0x0 r
AD7779 data sheet rev. 0 | page 88 of 97 channel 5 status register address: 0x051, reset: 0x00, name: ch5_err_reg channel 5 - reference detect erro r a in5- undervoltage error ain5+ overvoltage error a in5- overvoltage error ain5+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch5_err_ref_det (r) [4] ch5_err_ainm_uv (r) [1] ch5_err_ainp_ov (r) [3] ch5_err_ainm_ov (r) [2] ch5_err_ainp_uv (r) table 124. bit descriptions for ch5_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch5_err_ainm_uv channel 5ain5? undervoltage error 0x0 r 3 ch5_err_ainm_ov channel 5ain5? overvoltage error 0x0 r 2 ch5_err_ainp_uv channel 5ain5+ undervoltage error 0x0 r 1 ch5_err_ainp_ov channel 5ain5+ overvoltage error 0x0 r 0 ch5_err_ref_det channel 5reference detect error 0x0 r channel 6 status register address: 0x052, reset: 0x00, name: ch6_err_reg channel 6 - reference detect erro r a in6- undervoltage error ain6+ overvoltage error a in6- overvoltage error ain6+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch6_err_ref_det (r) [4] ch6_err_ainm_uv (r) [1] ch6_err_ainp_ov (r) [3] ch6_err_ainm_ov (r) [2] ch6_err_ainp_uv (r) table 125. bit descriptions for ch6_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch6_err_ainm_uv channel 6ain6? undervoltage error 0x0 r 3 ch6_err_ainm_ov channel 6ain6? overvoltage error 0x0 r 2 ch6_err_ainp_uv channel 6ain6+ undervoltage error 0x0 r 1 ch6_err_ainp_ov channel 6ain6+ overvoltage error 0x0 r 0 ch6_err_ref_det channel 6reference detect error 0x0 r
data sheet AD7779 rev. 0 | page 89 of 97 channel 7 status register address: 0x053, reset: 0x00, name: ch7_err_reg channel 7 - reference detect erro r a in7- undervoltage error ain7+ overvoltage error a in7- overvoltage error ain7+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch7_err_ref_det (r) [4] ch7_err_ainm_uv (r) [1] ch7_err_ainp_ov (r) [3] ch7_err_ainm_ov (r) [2] ch7_err_ainp_uv (r) table 126. bit descriptions for ch7_err_reg bits bit name settings description reset access 4 ch7_err_ainm_uv channel 7ain7? undervoltage error 0x0 r 3 ch7_err_ainm_ov channel 7ain7? overvoltage error 0x0 r 2 ch7_err_ainp_uv channel 7ain7+ undervoltage error 0x0 r 1 ch7_err_ainp_ov channel 7ain7+ overvoltage error 0x0 r 0 ch7_err_ref_det channel 7reference detect error 0x0 r channel 0/channel 1 dsp errors register address: 0x054, reset: 0x00, name: ch0_1_sat_err channel 0 - adc conversion has exceeded limits and has been clamped channel 1 - modulator output saturation error channel 0 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 1 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 0 - modulator output saturation error channel 1 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] ch0_err_output_sat (r) [5] ch1_err_mod_sat (r) [1] ch0_err_filter_sat (r) [4] ch1_err_filter_sat (r) [2] ch0_err_mod_sat (r) [3] ch1_err_output_sat (r) table 127. bit descriptions for ch0_1_sat_err bits bit name settings description reset access 5 ch1_err_mod_sat channel 1modulator output saturation error 0x0 r 4 ch1_err_filter_sat channel 1filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 r 3 ch1_err_output_sat channel 1adc conversion has exceeded limits and has been clamped 0x0 r 2 ch0_err_mod_sat channel 0modulator output saturation error 0x0 r 1 ch0_err_filter_sat channel 0filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 r 0 ch0_err_output_sat channel 0adc conversion has exceeded limits and has been clamped 0x0 r
AD7779 data sheet rev. 0 | page 90 of 97 channel 2/channel 3 dsp errors register address: 0x055, reset: 0x00, name: ch2_3_sat_err channel 2 - adc conversion has exceeded limits and has been clamped channel 3 - modulator output saturation error channel 2 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 3 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 2 - modulator output saturation error channel 3 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] ch2_err_output_sat (r) [5] ch3_err_mod_sat (r) [1] ch2_err_filter_sat (r) [4] ch3_err_filter_sat (r) [2] ch2_err_mod_sat (r) [3] ch3_err_output_sat (r) table 128. bit descriptions for ch2_3_sat_err bits bit name settings description reset access 5 ch3_err_mod_sat channel 3modulator output saturation error 0x0 r 4 ch3_err_filter_sat channel 3filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 r 3 ch3_err_output_sat channel 3adc conversion has exceeded limits and has been clamped 0x0 r 2 ch2_err_mod_sat channel 2modulator output saturation error 0x0 r 1 ch2_err_filter_sat channel 2filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 r 0 ch2_err_output_sat channel 2adc conversion has exceeded limits and has been clamped 0x0 r channel 4/channel 5 dsp errors register address: 0x056, reset: 0x00, name: ch4_5_sat_err channel 4 - adc conversion has exceeded limits and has been clamped channel 5 - modulator output saturation error channel 4 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 5 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 4 - modulator output saturation error channel 5 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] ch4_err_output_sat (r) [5] ch5_err_mod_sat (r) [1] ch4_err_filter_sat (r) [4] ch5_err_filter_sat (r) [2] ch4_err_mod_sat (r) [3] ch5_err_output_sat (r) table 129. bit descriptions for ch4_5_sat_err bits bit name settings description reset access 5 ch5_err_mod_sat channel 5modulator output saturation error 0x0 r 4 ch5_err_filter_sat channel 5filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 r 3 ch5_err_output_sat channel 5adc conversion has exceeded limits and has been clamped 0x0 r 2 ch4_err_mod_sat channel 4modulator output saturation error 0x0 r 1 ch4_err_filter_sat channel 4filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 r 0 ch4_err_output_sat channel 4adc conversion has exceeded limits and has been clamped 0x0 r
data sheet AD7779 rev. 0 | page 91 of 97 channel 6/channel 7 dsp errors register address: 0x057, reset: 0x00, name: ch6_7_sat_err channel 6 - adc conversion has exceeded limits and has been clamped channel 7 - modulator output saturation error channel 6 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 7 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 6 - modulator output saturation error channel 7 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] ch6_err_output_sat (r) [5] ch7_err_mod_sat (r) [1] ch6_err_filter_sat (r) [4] ch7_err_filter_sat (r) [2] ch6_err_mod_sat (r) [3] ch7_err_output_sat (r) table 130. bit descriptions for ch6_7_sat_err bits bit name settings description reset access 5 ch7_err_mod_sat channel 7modulator output saturation error 0x0 r 4 ch7_err_filter_sat channel 7filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 r 3 ch7_err_output_sat channel 7adc conversion has exceeded limits and has been clamped 0x0 r 2 ch6_err_mod_sat channel 6modulator output saturation error 0x0 r 1 ch6_err_filter_sat channel 6filter result has exceeded a reasonable level, before offset and gain calibration has been applied 0x0 r 0 ch6_err_output_sat channel 6adc conversion has exceeded limits and has been clamped 0x0 r channel 0 to channel 7 error register enable register address: 0x058, reset: 0xfe, name: chx_err_reg_en a dc conversion error test enable reference detect test enable filter saturation error test enable ainx+ overvoltage test enable enable error flag for modulator saturation ainx+ undervoltage test enable a inx- undervoltage test enable ainx- overvoltage test enable 0 0 1 1 2 1 3 1 4 1 5 1 6 1 7 1 [7] output_sat_test_en (r/w ) [0] ref_det_test_en (r/w ) [6] filter_sat_test_en (r/w) [1] ainp_ov_test_en (r/w) [5] mod_sat_test_en (r/w ) [2] ainp_uv_test_en (r/w ) [4] ainm_uv_test_en (r/w ) [3] ainm_ov_test_en (r/w ) table 131. bit descriptions for chx_err_reg_en bits bit name settings description reset access 7 output_sat_test_en adc conver sion error test enable 0x1 r/w 6 filter_sat_test_en filter saturation test enable 0x1 r/w 5 mod_sat_test_en enable error flag for modulator saturation 0x1 r/w 4 ainm_uv_test_en ainx? undervoltage test enable 0x1 r/w 3 ainm_ov_test_en ainx? overvoltage test enable 0x1 r/w 2 ainp_uv_test_en ainx+ undervoltage test enable 0x1 r/w 1 ainp_ov_test_en ainx+ overvoltage test enable 0x1 r/w 0 ref_det_test_en reference detect test enable 0x0 r/w
AD7779 data sheet rev. 0 | page 92 of 97 general errors register 1 address: 0x059, reset: 0x00, name: gen_err_reg_1 spi crc error a crc of the memory map contents is run periodically to check for errors spi invalid write address a crc of the fuse contents is run periodically to check for errors in the fuses spi invalid read address spi clock counter error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] spi_crc_err (r) [5] memmap_crc_err (r) [1] spi_invalid_write_err (r ) [4] rom_crc_err (r) [2] spi_invalid_read_err (r) [3] spi_clk_count_err (r) table 132. bit descriptions for gen_err_reg_1 bits bit name settings description reset access 5 memmap_crc_err a crc of the memory map contents is run periodically to check for errors 0x0 r 4 rom_crc_err a crc of the fuse contents is run pe riodically to check for er rors in the fuses 0x0 r 3 spi_clk_count_err spi clock counter error 0x0 r 2 spi_invalid_read_err spi invalid read address 0x0 r 1 spi_invalid_write_err spi invalid write address 0x0 r 0 spi_crc_err spi crc error 0x0 r general errors register 1 enable address: 0x05a, reset: 0x3e, name: gen_err_reg_1_en table 133. bit descriptions for gen_err_reg_1_en bits bit name settings description reset access 5 memmap_crc_test_en memory map crc test enable 0x1 r/w 4 rom_crc_test_en fuse crc test enable 0x1 r/w 3 spi_clk_count_test_en spi clock counter test enable 0x1 r/w 2 spi_invalid_read_test_en spi invalid read address test enable 0x1 r/w 1 spi_invalid_write_test_en spi invalid write address test enable 0x1 r/w 0 spi_crc_test_en spi crc error test enable 0x0 r/w
data sheet AD7779 rev. 0 | page 93 of 97 general errors register 2 address: 0x05b, reset: 0x00, name: gen_err_reg_2 dregcap power supply error reset detected areg2cap power supply error clock not switched over areg1cap power supply error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] dldo_psm_err (r) [5] reset_detected (r) [1] aldo2_psm_err (r) [4] ext_mclk_switch_err (r) [2] aldo1_psm_err (r) [3] reserved table 134. bit descriptions for gen_err_reg_2 bits bit name settings description reset access 5 reset_detected reset detected 0x0 r 4 ext_mclk_switch_err clock not switched over 0x0 r 2 aldo1_psm_err areg1cap power supply error 0x0 r 1 aldo2_psm_err areg2cap power supply error 0x0 r 0 dldo_psm_err dregcap power supply error 0x0 r general errors register 2 enable address: 0x05c, reset: 0x3c, name: gen_err_reg_2_en ldo psm trip test enable 11: 11 - run trip detect tes t on dregcap. 10: 10 - run trip detect test on areg2cap . 1: 01 - run trip detect tes t on areg1cap . 0: 00 - no trip detect test enabled. reset detect enable ldo psm tes t en 11: on all ldos. 11 - run power supply monitor test 10: on dregcap. 10 - run power supply monitor test 1: on aregxcap. 01 - run power supply monitor test 0: enabled. 00 - no power supply monitor test 0 0 1 0 2 1 3 1 4 0 5 1 6 0 7 0 [7:6] reserved [1:0] ldo_psm_trip_test_en (r/w) [5] reset_detect_en (r/w ) [3:2] ldo_psm_test_en (r/w) [4] reserved table 135. bit descriptions for gen_err_reg_2_en bits bit name settings description reset access 5 reset_detect_en reset detect enable 0x1 r/w 4 reserved reserved 0x1 r/w [3:2] ldo_psm_test_en ldo psm test en 0x3 r/w 0 00no power supply monitor test enabled. 1 01run power supply monitor test on aregxcap 10 10run power supply monitor test on dregcap 11 11run power supply monitor test on all ldos [1:0] ldo_psm_trip_test_en ldo psm trip test enable 0x0 r/w 0 00no trip detect test enabled 1 01run trip detect test on areg1cap 10 10run trip detect test on areg2cap 11 11run trip detect test on dregcap
AD7779 data sheet rev. 0 | page 94 of 97 error status register 1 address: 0x05d, reset: 0x00, name: status_reg_1 an error specific to ch0_err_reg is active set high if any error bit is high an error specific to ch1_err_reg is active a n error specific to ch4_err_reg is active an error specific to ch2_err_reg is active a n error specific to ch3_err_reg is active 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] err_loc_ch0 (r) [5] chip_error (r) [1] err_loc_ch1 (r) [4] err_loc_ch4 (r) [2] err_loc_ch2 (r) [3] err_loc_ch3 (r) table 136. bit descriptions for status_reg_1 bits bit name settings description reset access 5 chip_error set this bit high if any error bit is high 0x0 r 4 err_loc_ch4 an error specific to ch4_err_reg is active 0x0 r 3 err_loc_ch3 an error specific to ch3_err_reg is active 0x0 r 2 err_loc_ch2 an error specific to ch2_err_reg is active 0x0 r 1 err_loc_ch1 an error specific to ch1_err_reg is active 0x0 r 0 err_loc_ch0 an error specific to ch0_err_reg is active 0x0 r error status register 2 address: 0x05e, reset: 0x00, name: status_reg_2 an error specific to ch5_err_reg is active set high if any error bit is high an error specific to ch6_err_reg is active a n error specific to gen_err_reg_2 is active an error specific to ch7_err_reg is active a n error specific to gen_err_reg_1 is active 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] err_loc_ch5 (r) [5] chip_error (r) [1] err_loc_ch6 (r) [4] err_loc_gen2 (r) [2] err_loc_ch7 (r) [3] err_loc_gen1 (r) table 137. bit descriptions for status_reg_2 bits bit name settings description reset access 5 chip_error set high if any error bit is high 0x0 r 4 err_loc_gen2 an error specific to gen_err_reg_2 is active 0x0 r 3 err_loc_gen1 an error specific to gen_err_reg_1 is active 0x0 r 2 err_loc_ch7 an error specific to ch7_err_reg is active 0x0 r 1 err_loc_ch6 an error specific to ch6_err_reg is active 0x0 r 0 err_loc_ch5 an error specific to ch5_err_reg is active 0x0 r
data sheet AD7779 rev. 0 | page 95 of 97 error status register 3 address: 0x05f, reset: 0x00, name: status_reg_3 an error specific to ch0_1_sat_er r reg is active set high if any error bit is high an error specific to ch2_3_sat_er r reg is active fuse initialization is complete. device is ready to receive commands an error specific to ch4_5_sat_er r reg is active a n error specific to ch6_7_sat_err reg is active 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] err_loc_sat_ch0_1 (r) [5] chip_error (r) [1] err_loc_sat_ch2_3 (r) [4] init_complete (r) [2] err_loc_sat_ch4_5 (r) [3] err_loc_sat_ch6_7 (r) table 138. bit descriptions for status_reg_3 bits bit name settings description reset access 5 chip_error set high if any error bit is high. 0x0 r 4 init_complete fuse initialization is comple te. device is ready to receive commands. 0x0 r 3 err_loc_sat_ch6_7 an error specific to ch6_7_sat_err register is active. 0x0 r 2 err_loc_sat_ch4_5 an error specific to ch4_5_sat_err register is active. 0x0 r 1 err_loc_sat_ch2_3 an error specific to ch2_3_sat_err register is active. 0x0 r 0 err_loc_sat_ch0_1 an error specific to ch0_1_sat_err register is active. 0x0 r decimation rate (n) msb register address: 0x060, reset: 0x00, name: src_n_msb src n combined 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:4] reserved [3:0] src_n_all[11:8] ( r/w ) table 139. bit descriptions for src_n_msb bits bit name settings description reset access [3:0] src_n_all[11:8] src n combined 0x0 r/w decimation rate (n) lsb register address: 0x061, reset: 0x80, name: src_n_lsb src n combined 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 [7:0] src_n_all[7:0] (r/w ) table 140. bit descriptions for src_n_lsb bits bit name settings description reset access [7:0] src_n_all[7:0] src n combined 0x0 r/w
AD7779 data sheet rev. 0 | page 96 of 97 decimation rate (if) msb register address: 0x062, reset: 0x00, name: src_if_msb src if all 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] src_if_all[15:8] (r/w) table 141. bit descriptions for src_if_msb bits bit name settings description reset access [7:0] src_if_all[15:8] src if all 0x0 r/w decimation rate (if) lsb register address: 0x063, reset: 0x00, name: src_if_lsb src if all 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] src_if_all[7:0] (r/w) table 142. bit descriptions for src_if_lsb bits bit name settings description reset access [7:0] src_if_all[7:0] src if all 0x0 r/w src load source and load update register address: 0x064, reset: 0x00, name: src_update select which option to load an src update as s ert bit to load src regis ters into src 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7] src_load_source (r/w ) [0] src_load_update (r/w ) [6:1] reserved table 143. bit descriptions for src_update bits bit name settings description reset access 7 src_load_source selects which opti on to load an src update 0x0 r/w 0 src_load_update asserts bit to load src registers into src 0x0 r/w
data sheet AD7779 rev. 0 | page 97 of 97 outline dimensions 0.50 bsc bottom view top view pin 1 indicator exposed pad p i n 1 i n d i c a t o r 7.70 7.60 sq 7.50 0.45 0.40 0.35 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.18 02-12-2014-a 9.10 9.00 sq 8.90 0.20 min 7.50 ref compliant to jedec standards mo-220-wmmd 1 64 16 17 49 48 32 33 pkg-004396 figure 120. 64-lead lead frame chip scale package [lfcsp] 9 mm 9 mm body and 0.75 mm package height (cp-64-15) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD7779acpz ?40c to +125c 64-lead lead frame chip scale package [lfcsp] cp-64-15 AD7779acpz-rl ?40c to +125c 64-lead lead frame chip scale package [lfcsp] cp-64-15 1 z = rohs compliant part. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13295-0-2/16(0)

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